WorldCat Identities

Barbacci, Mario R.

Overview
Works: 72 works in 184 publications in 2 languages and 544 library holdings
Genres: Conference papers and proceedings  Handbooks and manuals 
Roles: Author, Other, Editor
Classifications: TK7888.3, 621.381952
Publication Timeline
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Most widely held works about Mario R Barbacci
 
Most widely held works by Mario R Barbacci
Computer hardware description languages and their applications : proceedings of the IFIP WG 10.2 Sixth International Symposium on Computer Hardware Description Languages and Their Applications, Pittsburgh, Pennsylvania, U.S.A., 23-25 May, 1983 by International symposium on computer hardware description languages and their applications <6. ; 1983 ; Pittsburgh>( Book )

19 editions published between 1983 and 1987 in English and held by 284 WorldCat member libraries worldwide

CONLAN Report by Robert Piloty( )

1 edition published in 1983 in English and held by 28 WorldCat member libraries worldwide

Automated exploration of the design space for register transfer (RT) systems by Mario R Barbacci( Book )

10 editions published between 1973 and 1987 in English and Undetermined and held by 10 WorldCat member libraries worldwide

Proceedings from the Second Workshop on Large-Grained Parallelism by Jeannette Marie Wing( Book )

4 editions published between 1987 and 1988 in English and held by 9 WorldCat member libraries worldwide

Durra : a task-level description language : preliminary reference manual by Mario R Barbacci( Book )

6 editions published in 1986 in English and Undetermined and held by 9 WorldCat member libraries worldwide

The Symbolic manipulation of computer descriptions : an introduction to ISPS by Mario R Barbacci( Book )

4 editions published in 1978 in English and held by 9 WorldCat member libraries worldwide

This report introduces the reader to the ISPS notation. Although some details have been excluded, it covers enough of the language to provide a 'reading' capability. Thus while this document in itself might not be sufficient to allow writing ISPS descriptions, it should be detailed enough to permit the reading and study of complex descriptions. Not all the features of the notation are presented in the examples. For a detailed explanation of the complete language the reader must consult the reference manual. The ISPS Computer Description Language, available from Departments of Computer Science and Electrical Engineering, Carnegie-Mellon University. There exists a compiler and simulator for ISPS. These programs are written in BLISS-10 and ron on a DEC PDP-10 Computer under either TOP-10, TOPS-20, or TENEX. (Author)
Some aspects of the symbolic manipulation of computer descriptions by Mario R Barbacci( Book )

5 editions published in 1974 in English and Undetermined and held by 8 WorldCat member libraries worldwide

Traditionally computer descriptive languages have been designed primarily for human communication and/or simulation. Due to this narrow range of applications the existing languages have taken on a strong degree of similarity. In this paper the authors present some applications in the realm of automatic design of both hardware and software where a computer description language could serve as the information exchange media between the user and the design automation system. The paper discusses an environment for research on the applications of computer descriptive languages, emphasizing the multiplicity of users and tasks that may coexist at any point in time. Some properties needed in a computer descriptive language are presented. A structured programming approach to hardware design is presented by example
ISP ; a language to describe instruction sets and other register transfer systems by Mario R Barbacci( Book )

5 editions published between 1970 and 1972 in English and held by 7 WorldCat member libraries worldwide

The paper describes the evolution of a notation, ISP (Instruction Set Processor), which was originally developed for defining the instruction set, data-types and operations and the interpreter of a computer, giving essentially the same information as in a programming manual. ISP has been used in a book (Bell and Newell, 1971), in programming manuals, and papers to describe many computers. As part of the evolution of the language, much consideration has been given to the readability and simplicity of the notation as a descriptive tool, as well as to some other properties such as extensibility and fidelity, required by the notation as a design tool. ISP has also been extended (evolved) to handle Register Transfer (RT) systems for description, simulation and design purposes, including a flow chart form used in the Register Transfer Module System (Bell, Grason and Newell, 1972). For RT design it has been necessary to incorporate additional facilities to describe the switching circuits (i.e. combinational and sequential components). (Author)
Specification, evaluation, and validation of computer architectures using instruction set processor descriptions by Mario R Barbacci( Book )

2 editions published in 1979 in English and held by 7 WorldCat member libraries worldwide

Instruction set processor specifications (ISPS) : the notation and its applications by Mario R Barbacci( Book )

2 editions published in 1979 in English and held by 7 WorldCat member libraries worldwide

CONLAN report by Robert Piloty( Book )

7 editions published in 1983 in English and Italian and held by 6 WorldCat member libraries worldwide

Specifying functional and timing behavior for real-time applications by Mario R Barbacci( Book )

4 editions published in 1986 in English and held by 6 WorldCat member libraries worldwide

We present a notation and a methodology for specifying the functional and timing behavior of real-time applications for a heterogeneous machine. In our methodology we build upon well-defined, though isolated, pieces of previous work: Larch and Real Time Logic. In our notation, we strive to keep separate the functional specification from the timing specification so that a task's functionality can be understood independent of its timing behavior. We show that while there is a clean separation of concerns between these two specifications, the semantics of both pieces as well as their combination are simple. Keywords: syntax; queueing theory
Ada as a hardware description language : an initial report by Mario R Barbacci( Book )

5 editions published between 1984 and 1985 in English and Undetermined and held by 6 WorldCat member libraries worldwide

This paper reports on our initial results in using Ada as a Hardware Description Language. Ada provides abstraction mechanisms to support the development of large software systems. Separate compilation as well as nesting of packages, tasks, and subprograms allow the construction of modular systems communicating through well defined interfaces. The complexity of modern chips (e.g. those proposed in the VHSIC program) will require the use of those features that make Ada a good language for programming-in-the-large. The key to our approach is establishing a writing style appropriate to the objective of describing both the behavior and the structure of hardware components. We model a hardware system as an ensemble of typed objects, where each object is an instance of an abstract data type. The type definition and the associated operations are encapsulated by a corresponding package. In this paper we illustrate our approach through a series of examples, building up a hypothetical hierarchy of hardware components. We conclude by discussing ways to describe arbitrarily complex simulation models and synthesis styles. (Author)
Representing time and space in an object oriented hardware description language by Mario R Barbacci( Book )

5 editions published in 1985 in English and held by 6 WorldCat member libraries worldwide

Hardware description languages (HDLs) will clearly play a vital role in the comprehensive VLSI design tools of the future. Now that the requirements for such HDLs are becoming better understood it is becoming increasingly evident that the central issues are abstraction, modularity, and complexity management --- the same issues faced by designers of large scale software systems, rather than low-level technological details (although these must ultimately be served as well). Consequently, we argue that Ada, constituting the most advanced, carefully conceived, and (soon to be) widely available modern high-order programming language, forms not only an adequate but a compelling choice as an HDL. Specifically, Ada offers separate compilation as well as nesting of packages, tasks, and subprograms. These, and other important features of Ada, allow the construction of modular systems communicating through well defined interfaces. This paper demonstrates how placement and routing information can be incorporated into Ada hardware descriptions; another paper (Barbacci et al., 1985) shows how component and signal propagation delays over carriers are also incorporated into the same hardware descriptions. (Author)
The ISPS computer description language : the symbolic manipulation of computer descriptions( Book )

4 editions published between 1970 and 1980 in English and held by 6 WorldCat member libraries worldwide

Durra : a task-level description language reference manual by Mario R Barbacci( Book )

3 editions published between 1989 and 1992 in English and held by 5 WorldCat member libraries worldwide

Abstract: "Durra is a language designed to support the development of large-grained parallel programming applications. These applications are often computation-intensive, or have real-time requirements that require efficient concurrent execution of multiple tasks, devoted to specific pieces of the application. During execution time the application tasks run on possibly separate processors, and communicate with each other by sending messages of different types across various communication links. The application developer is responsible for prescribing a way to manage all of these resources. We call this prescription a task-level application description
The Durra runtime environment by Mario R Barbacci( Book )

2 editions published in 1988 in English and held by 5 WorldCat member libraries worldwide

Durra is a language designed to support PMS-level programming. PMS stands for Processor-Memory-Switch, the name of the highest level in th hierarchy of digital systems. An application or PMS-level program is written in Durra as a set of task descriptions and type declarations that prescribes a way to manage the resources of a heterogeneous machine network. The application describes the tasks to be instantiated and executed as concurrent processes. The types of data to be exchanged by the processes, and the intermediate queues required to store the data as they move from producer to consumer processes. The report describes the Durra Runtime Environment. The environment consists of three active components: the application tasks, the Durra server, and the Durra scheduler. After compiling the type declarations, the component task descriptions, and the application description, the application can be executed by starting an instance of the server on each processor, starting an instance of the scheduler on one of the processors, and downloading the component task implementations (i.e., the programs) to the processors. the scheduler receives an an argument the name of the file containing the scheduler program generated by the compilation of the application description. This step initiates the execution of the application. (kr)
MasterTask : the durra task emulator by Mario R Barbacci( Book )

2 editions published in 1988 in English and held by 5 WorldCat member libraries worldwide

Durra is a language designed to support the construction of distributed applications using concurrent, coarse-grain tasks running on networks of heterogeneous processors. An application written in Durra describes the tasks to be instantiated and executed as concurrent processes, the types of data to be exchanged by the processes, and the intermediate queues required to store the data as they move from producer to consumer processes. The tasks and types available to an application developer are described by a collection of Durra task descriptions and type declarations stored in a library. One of the components of a task description is a specification of the external timing behavior of the task. It describes the sequence of input and output port operations and the amount of processing time spent between port operations. This report describes MasterTask, a program that can emulate any task in an application by interpreting the timing expression describing the behavior of the task, performing the input and output operations in the proper sequence and at the proper time. MasterTask is useful to both application developers and task developers. Application developers can build early prototypes of an application by using MasterTask as a substitute for task implementations that have yet to be written. Task developers can experiment with and evaluate proposed changes in task behavior or performance by rewriting and reinterpreting the corresponding timing expression. Keywords: Real time; Computer networks; Task specification languages. (kr)
Evaluation of alternative computer architectures( Book )

2 editions published in 1977 in English and held by 5 WorldCat member libraries worldwide

The Computer Family Architecture (CFA) Selection Committee was organized to select a proven, well-known computer architecture, in addition to several widely used military computer architectures, as the basis of the future series of Military Computer Family (MCF) computers. The set of four papers that make up this report provide an Overview of the work of the CFA Committee and a detailed discussion of the technical methods used to quantitatively evaluate the alternative computer architectures under consideration. As the first paper describes, support software availability, life cycle costs, and architecture licensing, in addition to architectural efficiency, were considered in the final evaluation process. As a result of this process, the CFA Committee ranked the three architecture finalists in the following order: the DEC PDP-11, the IBM System/370, and the Interdata 8/32. The MCF project is now working on the specification of a new standard architecture for military applications based on the PDP-11. In addition, the MCF project is working on more clearly specifying the most widely used existing military computer architectures to enable future reimplementations of these architectures in new technologies
The Symbolic Manipulation of Computer Descriptions: ISPL Compiler and Simulator by Mario R Barbacci( Book )

4 editions published in 1976 in English and Undetermined and held by 5 WorldCat member libraries worldwide

The compiler described in this manual will translate programs written in a subset of ISP into register transfer level instructions. The code thus generated could be used for the implementation of wiring list generators, simulators, or other Computer Aided Design applications. This manual describes the syntax and semantics of the language (ISPL) accepted by the compiler. The simulator described in this manual will interpret the output of the ISPL compiler, the RTM code, thus allowing the users a generalized computer architecture simulation facility. This manual describes the commands available to the users
 
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CONLAN report
Alternative Names
Barbacci, M.

Barbacci, M. (Mario)

Barbacci, M. R.

Barbacci, M. R. (Mario R.)

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