WorldCat Identities

Kung, H. T.

Overview
Works: 107 works in 223 publications in 1 language and 2,087 library holdings
Genres: Conference proceedings 
Roles: Editor, Author of introduction
Classifications: TK5105, 004.66
Publication Timeline
Key
Publications about  H. T Kung Publications about H. T Kung
Publications by  H. T Kung Publications by H. T Kung
Most widely held works by H. T Kung
Traffic management for high-speed networks by H. T Kung ( )
8 editions published in 1997 in English and held by 1,404 WorldCat member libraries worldwide
VLSI systems and computations by H. T Kung ( Book )
11 editions published in 1981 in English and held by 315 WorldCat member libraries worldwide
An optimality theory of concurrency control for databases by H. T Kung ( Book )
9 editions published between 1979 and 1980 in English and Undetermined and held by 19 WorldCat member libraries worldwide
A concurrency control mechanism (or a scheduler) is the component of a database system that safeguards the consistency of the database in the presence of interleaved accesses and update requests. We formally show that the performance of a scheduler, i.e., the amount of parallelism that it supports, depends explicitly upon the amount of information that is available to the scheduler. We point out that most previous work on concurrency control is simply concerned with specific points of the base trade-off between performance and information. In fact, several of these approaches are shown to be optimal for the amount of information that they use. (Author)
Why systolic architectures? by H. T Kung ( Book )
5 editions published between 1981 and 1982 in English and Undetermined and held by 10 WorldCat member libraries worldwide
Sorting on a mesh-connected parallel computer by C. D Thompson ( Book )
2 editions published in 1976 in English and held by 10 WorldCat member libraries worldwide
Two algorithms are presented for sorting M to the 2nd power elements on an nxn mesh-connected processor array that require O(n) routing and comparison steps. The best previous algorithm takes time O(n log n). The algorithms of this paper are shown to be optimal in time within small constant factors. Extensions to higher-dimensional mesh-connected processor arrays are also given. (Author)
Systolic (VLSI) arrays for relational database operations by H. T Kung ( Book )
3 editions published between 1979 and 1980 in English and held by 9 WorldCat member libraries worldwide
This paper proposes the use of VLSI technology to perform relational database operations directly in hardware. It is shown that relational computations, such as intersection, remove-duplicates, union, join, and division, can all be pipelined elegantly and efficiently on networks of processors having an array structure. These (systolic) processor arrays are readily and cost-effectively implementable with present technology, due to the extreme simplicity of their processors, and the high regularity of their interconnection structures. (Author)
An efficient parallel garbage collection system and its correctness proof by H. T Kung ( Book )
3 editions published in 1977 in English and Undetermined and held by 9 WorldCat member libraries worldwide
An efficient system to perform garbage collection in parallel with list operations is proposed and its correctness is proven. The system consists of two independent processes sharing a common memory. One process is performed by the list processor (LP) for list processing and the other by the garbage collector (GC) for marking active nodes and collecting garbage nodes. The system is derived by using both the correctness and efficiency arguments. Assuming that memory references are indivisible the system satisfies the following properties: No critical sections are needed in the entire system. The time to perform the marking phase by the GC is independent of the size of memory, but depends only on the number of active nodes. Nodes on the free list need not be marked during the marking phase by the GC. Minimum overheads are introduced to the LP. Only two extra bits for encoding four colors are needed for each node. Efficiency results show that the parallel system is usually significantly more efficient in terms of storage and time than the sequential stack algorithm. (Author)
A systolic algorithm for integer GCD computation by R. P Brent ( Book )
6 editions published in 1984 in English and Undetermined and held by 9 WorldCat member libraries worldwide
Abstract: "We show that the greatest common divisor of two n-bit integers (given in the usual binary representation) can be computed in time O(n) on a linear array of O(n) identical systolic cells, each of which is a finite-state machine with connections to its nearest neighbours."
Synchronized and asynchronous parallel algorithms for multiprocessors by H. T Kung ( Book )
2 editions published in 1976 in English and held by 8 WorldCat member libraries worldwide
Parallel algorithms for multiprocessors are classified into synchronized and asynchronous algorithms. Important characteristics with respect to the design and analysis of the two types of algorithms are identified and discussed. Several examples of the two types of algorithms are considered in depth
VLSI systems and computations : [papers pres. at Carnegie-Mellon Univ. Conference on VLSI Systems and Computations, Oct. 19-21, 1981] ( Book )
2 editions published in 1981 in Undetermined and English and held by 8 WorldCat member libraries worldwide
Systolic algorithms for the CMU Warp processor by H. T Kung ( Book )
3 editions published in 1984 in English and Undetermined and held by 8 WorldCat member libraries worldwide
The prototype has 10 cells, each of which is capable of performing 10 million floating-point operations per second (10 MFLOPS) and is build on a single board using only off-the-shelf components. This 10-cell processor for example can process 1024-point complex FFTs at a rate of one FFT every 600 [mu]s. Under program control, the same processor can perform many other primitive computations in signal, image and vision processing, including two-dimensional convolution and complex matrix multiplication, at a rate of 100 MFLOPS. Together with another processor capable of performing divisions and square roots, the processor can also efficiently carry out a number of difficult matrix operations such as solving covariant linear systems, a crucial computation in real-time adaptive signal processing. This paper outlines the architecture of the Warp processor and describes how the signal processing tasks are implemented on the processor."
Comprehensive evaluation of a two-dimensional configurable array by O Menzilcioglu ( Book )
2 editions published between 1989 and 1990 in English and held by 7 WorldCat member libraries worldwide
Abstract: "This paper presents the evaluation of a highly configurable architecture for two-dimensional (2D) arrays of powerful processors. The evaluation is based on an array of Warp cells, a powerful processor developed at Carnegie Mellon and manufactured by General Electric, and uses real application programs. The evaluation covers the areas of configurability, array survivability, and performance degradation. The software and algorithms developed for the evaluation are also discussed. The results based on simulations of small and medium size arrays (up to 16x16), show that a high degree of configurability, and array survivability can be achieved with little impact on program performance."
Special-purpose devices for signal and image processing : an opportunity in VLSI by H. T Kung ( Book )
3 editions published in 1980 in English and Undetermined and held by 7 WorldCat member libraries worldwide
Based on the systolic array approach, new designs of special-purpose devices for filtering, correlation, convolution, and discrete Fourier transform are proposed and discussed. It is argued that because of high degrees of simplicity, regularity and concurrency inherent to these designs, their VLSI implementation will be cost effective. (Author)
All algebraic functions can be computed fast by H. T Kung ( Book )
3 editions published in 1976 in English and Undetermined and held by 7 WorldCat member libraries worldwide
The expansions of algebraic functions can be computed 'fast' using the Newton Polygon Process and any 'normal' iteration. Let M(j) be the number of operations sufficient to multiply two jth degree polynomials. It is shown that the first N terms of an expansion of any algebraic function defined by an nth degree polynomial can be computed in O(n(M(N)) operations, while the classical method needs O(N sup n) operations. Among the numerous applications of algebraic functions are symbolic mathematics and combinatorial analysis. Reversion, reciprocation, and nth root of a polynomial are all special cases of algebraic functions
Fault-tolerance and two-level pipelining in VLSI systolic arrays by H. T Kung ( Book )
3 editions published in 1983 in English and Undetermined and held by 7 WorldCat member libraries worldwide
This paper addresses two important issues in systolic array designs: fault-tolerance and two-level pipelining. The proposed 'systolic' fault-tolerant scheme maintains the original data flow pattern by bypassing defective cells with a few registers. As a result, many of the desirable properties of systolic arrays (such as local and regular communication between cells) are preserved. Two-level pipelining refers to the use of pipelined functional units in the implementation of systolic cells. This paper addresses the problem of efficiently utilizing pipelined units to increase the overall system throughput. We show that both of these problems can be reduced to the same mathematical problem of incorporating extra delays on certain data paths in originally correct systolic designs. We introduce the mathematical notion of a cut which enables us to handle this problem effectively. The results obtained by applying the techniques described in this paper are encouraging. When applied to systolic arrays without feedback cycles, the arrays can tolerate large numbers of failures (with the addition of very little hardware) while maintaining the original throughput. Furthermore, all of the pipeline stages in the cells can be kept fully utilized through the addition of a small number of delay registers. However, adding delays to systolic arrays with cycles typically induces a significant decrease in throughput. In response to this, we have derived a new class of systolic algorithms in which the data cycle around a ring of processing cells
The area-time complexity of Binary multiplication by R. P Brent ( Book )
3 editions published in 1979 in English and Undetermined and held by 7 WorldCat member libraries worldwide
We consider the problem of performing multiplication of n-bit binary numbers on a chip. Let A denote the chip area, and T the time required to perform multiplication. Using a model of computation which is a realistic approximation to current and anticipated VLSI technology, we show that (A/A sub 0) (T/T sub 0) to the 2 alpha power> or = n to the (1 + alpha) power for all alpha is an element (0, 1), where A sub 0 and T sub 0 are positive constants which depend on the technology but are independent of n. The exponent 1 + alpha is the best possible. A consequence is that binary multiplication is 'harder' than binary addition if AT to the 2 alpha power is used as a complexity measure for any alpha> or = 0. (Author)
MISE, Machine for In-System Evaluation of custom VLSI chips ( Book )
3 editions published in 1982 in English and held by 7 WorldCat member libraries worldwide
This paper identifies some of the key research problems that one encounters in specifying, designing, testing and demonstrating a custom chip in relation to the application system in which it will be used, and proposes a system called MISE(Machine For In-System Evaluation) to be a solution to the issues raised
Concurrent manipulation of binary search trees by H. T Kung ( Book )
3 editions published in 1979 in English and Undetermined and held by 6 WorldCat member libraries worldwide
The concurrent manipulation of a binary search tree is considered in this paper. The systems presented can support any number of concurrent processes which perform searching, insertion, deletion, and rotation(reorganization) on the tree, but allow any process to lock only a constant number of nodes at any time. Also, in the systems, searches are essentially never blocked. The concurrency control techniques introduced in the paper include the use of special nodes and pointers to redirect searches, and the use of copies of sections of the tree to introduce many changes simultaneously and therefore avoid unpredictable interleaving. Methods developed in this paper may provide new insights to other problems in the area of concurrent database manipulation. (Author)
Deadlock avoidance for systolic communication by H. T Kung ( Book )
3 editions published in 1987 in English and Undetermined and held by 6 WorldCat member libraries worldwide
Let's design algorithms for VLSI systems by H. T Kung ( Book )
2 editions published in 1979 in English and held by 6 WorldCat member libraries worldwide
 
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Alternative Names
Kung, Hsing T.
Languages
English (66)
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