Leiserson, Charles Eric
Overview
Works:  85 works in 246 publications in 6 languages and 2,143 library holdings 

Genres:  Conference proceedings 
Roles:  Author, Editor 
Classifications:  QA76.6, 005.1 
Publication Timeline
.
Most widely held works by
Charles Eric Leiserson
Introduction to algorithms
by
Thomas H Cormen(
Book
)
99 editions published between 1989 and 2014 in 6 languages and held by 1,355 WorldCat member libraries worldwide
Some books on algorithms are rigorous but incomplete; others cover masses of material but lack rigor. Introduction to Algorithms uniquely combines rigor and comprehensiveness. The book covers a broad range of algorithms in depth, yet makes their design and analysis accessible to all levels of readers. Each chapter is relatively selfcontained and can be used as a unit of study. The algorithms are described in English and in a pseudocode designed to be readable by anyone who has done a little programming. The explanations have been kept elementary without sacrificing depth of coverage or mathematical rigor.  The first edition became a widely used text in universities worldwide as well as the standard reference for professionals. The second edition featured new chapters on the role of algorithms, probabilistic analysis and randomized algorithms, and linear programming. The third edition has been revised and updated throughout. It includes two completely new chapters, on van Emde Boas trees and multithreaded algorithms, and substantial additions to the chapter on recurrences (now called "DivideandConquer"). It features improved treatment of dynamic programming and greedy algorithms and a new notion of edgebased flow in the material on flow networks. Many new exercises and problems have been added for this edition
99 editions published between 1989 and 2014 in 6 languages and held by 1,355 WorldCat member libraries worldwide
Some books on algorithms are rigorous but incomplete; others cover masses of material but lack rigor. Introduction to Algorithms uniquely combines rigor and comprehensiveness. The book covers a broad range of algorithms in depth, yet makes their design and analysis accessible to all levels of readers. Each chapter is relatively selfcontained and can be used as a unit of study. The algorithms are described in English and in a pseudocode designed to be readable by anyone who has done a little programming. The explanations have been kept elementary without sacrificing depth of coverage or mathematical rigor.  The first edition became a widely used text in universities worldwide as well as the standard reference for professionals. The second edition featured new chapters on the role of algorithms, probabilistic analysis and randomized algorithms, and linear programming. The third edition has been revised and updated throughout. It includes two completely new chapters, on van Emde Boas trees and multithreaded algorithms, and substantial additions to the chapter on recurrences (now called "DivideandConquer"). It features improved treatment of dynamic programming and greedy algorithms and a new notion of edgebased flow in the material on flow networks. Many new exercises and problems have been added for this edition
Areaefficient VLSI computation
by
Charles Eric Leiserson(
Book
)
15 editions published between 1981 and 1987 in English and Undetermined and held by 320 WorldCat member libraries worldwide
The two parts of this thesis address two measures of efficiency. Part 1 analyzes systolic systems which marry the ideas of pipelining and multiprocessing in a single framework of design. Part II looks at the layout of their communication paths. Although the two parts fit together, it should be understood that the ideas in each stand alone. The results of Part I can be applied to systems which are not systolic, and even systems which are not assembled on integrated circuits. The layout results of Part II can be applied to more general communication structures than graphs of systolic systems, and the ideas for representing layouts can be used in other routing algorithms
15 editions published between 1981 and 1987 in English and Undetermined and held by 320 WorldCat member libraries worldwide
The two parts of this thesis address two measures of efficiency. Part 1 analyzes systolic systems which marry the ideas of pipelining and multiprocessing in a single framework of design. Part II looks at the layout of their communication paths. Although the two parts fit together, it should be understood that the ideas in each stand alone. The results of Part I can be applied to systems which are not systolic, and even systems which are not assembled on integrated circuits. The layout results of Part II can be applied to more general communication structures than graphs of systolic systems, and the ideas for representing layouts can be used in other routing algorithms
Advanced research in VLSI : proceedings of the fourth MIT conference, April 79, 1986
by
Massachusetts Institute of Technology(
Book
)
6 editions published in 1986 in English and Undetermined and held by 228 WorldCat member libraries worldwide
6 editions published in 1986 in English and Undetermined and held by 228 WorldCat member libraries worldwide
Retiming synchronous circuitry
by
Charles Eric Leiserson(
Book
)
8 editions published between 1986 and 1988 in English and Undetermined and held by 26 WorldCat member libraries worldwide
This paper describes a circuit transformation called retiming in which registers are added at some points in a circuit and removed from others in such a way that he functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex set V is a collection of combinational logic elements and the edge set E is the set of interconnections, each of which may pass through zero or more registers. We give an algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomialtime solvable. This result yields a polynomialtime optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a characterization of optimal retiming based on an efficiently solvable mixedinteger linear programming problem. Keywords include: Digital circuitry, Graph theory, Linear programming, Network flow, Optimization, Pipelining, Propagation delay, Retiming, Synchronous circuitry, and Systolic circuits. (RH)
8 editions published between 1986 and 1988 in English and Undetermined and held by 26 WorldCat member libraries worldwide
This paper describes a circuit transformation called retiming in which registers are added at some points in a circuit and removed from others in such a way that he functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex set V is a collection of combinational logic elements and the edge set E is the set of interconnections, each of which may pass through zero or more registers. We give an algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomialtime solvable. This result yields a polynomialtime optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a characterization of optimal retiming based on an efficiently solvable mixedinteger linear programming problem. Keywords include: Digital circuitry, Graph theory, Linear programming, Network flow, Optimization, Pipelining, Propagation delay, Retiming, Synchronous circuitry, and Systolic circuits. (RH)
Optimizing synchronous systems
by
Charles Eric Leiserson(
Book
)
5 editions published between 1981 and 1982 in English and Undetermined and held by 17 WorldCat member libraries worldwide
5 editions published between 1981 and 1982 in English and Undetermined and held by 17 WorldCat member libraries worldwide
Optimal placement for river routing
by
Charles Eric Leiserson(
Book
)
5 editions published between 1981 and 1987 in English and held by 11 WorldCat member libraries worldwide
5 editions published between 1981 and 1987 in English and held by 11 WorldCat member libraries worldwide
Waferscale integration of systolic arrays
by
Frank Thomson Leighton(
Book
)
4 editions published between 1983 and 1985 in English and held by 10 WorldCat member libraries worldwide
VLSI technologies are fast developing waferscale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind waferscale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating waferscale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NPcomplete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, faulttolerant systems and planar geometry
4 editions published between 1983 and 1985 in English and held by 10 WorldCat member libraries worldwide
VLSI technologies are fast developing waferscale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind waferscale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating waferscale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NPcomplete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, faulttolerant systems and planar geometry
A mixedinteger linear programming problem which is efficiently solvable
by
Charles Eric Leiserson(
Book
)
3 editions published between 1985 and 1987 in English and held by 9 WorldCat member libraries worldwide
Much research has centered on the problem of finding shortest paths in graphs. It is well known that there is a direct correspondence between the single source shortestpaths problem and the following simple linear programming problems: Let S be a set of linear inequalities of the form x sub j  x sub i <or = (a sub ij, where the x sub i are unknowns and the a sub ij are given real constants. Determine a set of values for the x sub i such that the inequalities in S are satisfied, or determine that no such values exist. This paper considers the mixedinteger linear programming variant of this problem in which some (but not necessarily all) of the x sub i are required to be integers. The problem arises in the context of synchronous circuit optimization but it has applications to PERT scheduling and VLSI layout compaction as well. Keywords: Algorithms, Combinatorial optimization
3 editions published between 1985 and 1987 in English and held by 9 WorldCat member libraries worldwide
Much research has centered on the problem of finding shortest paths in graphs. It is well known that there is a direct correspondence between the single source shortestpaths problem and the following simple linear programming problems: Let S be a set of linear inequalities of the form x sub j  x sub i <or = (a sub ij, where the x sub i are unknowns and the a sub ij are given real constants. Determine a set of values for the x sub i such that the inequalities in S are satisfied, or determine that no such values exist. This paper considers the mixedinteger linear programming variant of this problem in which some (but not necessarily all) of the x sub i are required to be integers. The problem arises in the context of synchronous circuit optimization but it has applications to PERT scheduling and VLSI layout compaction as well. Keywords: Algorithms, Combinatorial optimization
The organization of permutation architectures with bussed interconnections
by
Joe Kilian(
Book
)
4 editions published between 1987 and 1989 in English and held by 8 WorldCat member libraries worldwide
This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to pointtopoint interconnections, we show the number of pins per chip can often be reduced. We also consider uniform permutation architectures that realize permutations in several clock ticks, instead of one, and show that further savings in the number of pins per chip can be obtained. Keywords: Barrel shifter, Bussed interconnections, Cyclic shifter, Difference cover, Difference set, Group theory, Permutation, Permutation architecture, Projective plane, Specialpurpose architecture, Uniform architecture
4 editions published between 1987 and 1989 in English and held by 8 WorldCat member libraries worldwide
This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to pointtopoint interconnections, we show the number of pins per chip can often be reduced. We also consider uniform permutation architectures that realize permutations in several clock ticks, instead of one, and show that further savings in the number of pins per chip can be obtained. Keywords: Barrel shifter, Bussed interconnections, Cyclic shifter, Difference cover, Difference set, Group theory, Permutation, Permutation architecture, Projective plane, Specialpurpose architecture, Uniform architecture
VLSI theory and parallel supercomputing
by
Charles Eric Leiserson(
Book
)
1 edition published in 1989 in English and held by 7 WorldCat member libraries worldwide
1 edition published in 1989 in English and held by 7 WorldCat member libraries worldwide
Systolic Arrays for (VLSI)
by
H. T Kung(
Book
)
4 editions published between 1978 and 1979 in English and Undetermined and held by 6 WorldCat member libraries worldwide
A systolic system is a network of processors which rhythmically compute and pass data through the system. Physiologists use the work 'systole' to refer to the rhythmically recurrent contraction of the heart and arteries which pulses blood through the body. In a systolic computing system, the function of a processor is analogous to that of the heart. Every processor regularly pumps data in and out, each time performing some short computation, so that a regular flow of data is kept up in the network. Many basic matrix computations can be pipelined elegantly and efficiently on systolic networks having an array structure. As an example, hexagonally connected processors can optimally perform matrix multiplication. Surprisingly, a similar systolic array can compute the LUdecomposition of a matrix. These systolic arrays enjoy simple and regular communication paths, and almost all processors used in the networks are identical. As a result, special purpose hardware devices based on systolic arrays can be built inexpensively using the VLSI technology. (Author)
4 editions published between 1978 and 1979 in English and Undetermined and held by 6 WorldCat member libraries worldwide
A systolic system is a network of processors which rhythmically compute and pass data through the system. Physiologists use the work 'systole' to refer to the rhythmically recurrent contraction of the heart and arteries which pulses blood through the body. In a systolic computing system, the function of a processor is analogous to that of the heart. Every processor regularly pumps data in and out, each time performing some short computation, so that a regular flow of data is kept up in the network. Many basic matrix computations can be pipelined elegantly and efficiently on systolic networks having an array structure. As an example, hexagonally connected processors can optimally perform matrix multiplication. Surprisingly, a similar systolic array can compute the LUdecomposition of a matrix. These systolic arrays enjoy simple and regular communication paths, and almost all processors used in the networks are identical. As a result, special purpose hardware devices based on systolic arrays can be built inexpensively using the VLSI technology. (Author)
Areaefficient graph layouts (for VLSI)
by
Charles Eric Leiserson(
Book
)
1 edition published in 1980 in English and held by 6 WorldCat member libraries worldwide
1 edition published in 1980 in English and held by 6 WorldCat member libraries worldwide
8th Annual ACM symposium on parallel algorithms and architectures
(
Book
)
1 edition published in 1996 in English and held by 6 WorldCat member libraries worldwide
1 edition published in 1996 in English and held by 6 WorldCat member libraries worldwide
Randomized routing on fattrees
by R. I Greenberg(
Book
)
2 editions published between 1985 and 1986 in English and held by 6 WorldCat member libraries worldwide
Fattrees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fattree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda = omega (lg n lg lg n) on a fattree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is o (lambda) with probability 10(1/n). The best previous bound was 0(lambda lg n) for the offline problem where switch settings can be determined in advance. In a VLSIlike model where hardware cost is equated with physical volume, we use the routing algorithm to demonstrate that fattrees are universal routing networks in the sense that any routing network can be efficiently simulated by a fattree of comparable hardware cost. (Author)
2 editions published between 1985 and 1986 in English and held by 6 WorldCat member libraries worldwide
Fattrees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fattree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda = omega (lg n lg lg n) on a fattree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is o (lambda) with probability 10(1/n). The best previous bound was 0(lambda lg n) for the offline problem where switch settings can be determined in advance. In a VLSIlike model where hardware cost is equated with physical volume, we use the routing algorithm to demonstrate that fattrees are universal routing networks in the sense that any routing network can be efficiently simulated by a fattree of comparable hardware cost. (Author)
A spaceefficient algorithm for finding the connected components of rectangles in the plane
by
Charles Eric Leiserson(
Book
)
1 edition published in 1987 in English and held by 6 WorldCat member libraries worldwide
1 edition published in 1987 in English and held by 6 WorldCat member libraries worldwide
Systolic priority queues
by
Charles Eric Leiserson(
Book
)
1 edition published in 1979 in English and held by 6 WorldCat member libraries worldwide
1 edition published in 1979 in English and held by 6 WorldCat member libraries worldwide
Communicationefficient parallel graph algorithms
by
Charles Eric Leiserson(
Book
)
1 edition published in 1986 in English and held by 6 WorldCat member libraries worldwide
1 edition published in 1986 in English and held by 6 WorldCat member libraries worldwide
How to assemble tree machines
by
Sandeep Nautam Bhatt(
Book
)
2 editions published between 1982 and 1984 in English and held by 5 WorldCat member libraries worldwide
2 editions published between 1982 and 1984 in English and held by 5 WorldCat member libraries worldwide
A hyperconcentrator switch for routing bitserial messages
by
Thomas H Cormen(
Book
)
1 edition published in 1987 in English and held by 5 WorldCat member libraries worldwide
1 edition published in 1987 in English and held by 5 WorldCat member libraries worldwide
A timing analysis of levelclocked circuitry
by A. T Ishii(
Book
)
3 editions published between 1990 and 1992 in English and held by 5 WorldCat member libraries worldwide
This paper presents an algorithm for verifying proper timing in VLSI circuits where latches are controlled by the levels (high or low) of the controlling clocks rather than the transitions (edges) of the clocks. Such levelclocked circuits are frequently used in MOS VLSI design. A levelclocked circuit is modeled as a graph G = (V, E), where V consists of componentslatches and functional elementsand E represents intercomponent connections. The algorithm verifies the proper timing of a circuit in worstcase O(V/E) time and O(V + E) space. Our analysis decouples the problem of generating timing constraints from the problem of efficiently checking them. We show how various base step functions can be used to provide sufficient conditions for a circuit to operate properly, and we provide a new base step function which is less pessimistic than those used in previous timing verifiers, yet correctly handles timing constraints that are cyclic or extend across the boundaries of multiple clock phases or cycles. The base step function is used to derive a computational expansion of the circuit from which a collection of simple linear constraints are derived. These constraints can be efficiently checked using standard graph algorithms. VLSI systems, Levelclocking, Timing constraints, Timing analysis, Timing verification, Computational expansions, Deltaconstraints, Formal modeling, Graph algorithm applications, Algorithmic techniques
3 editions published between 1990 and 1992 in English and held by 5 WorldCat member libraries worldwide
This paper presents an algorithm for verifying proper timing in VLSI circuits where latches are controlled by the levels (high or low) of the controlling clocks rather than the transitions (edges) of the clocks. Such levelclocked circuits are frequently used in MOS VLSI design. A levelclocked circuit is modeled as a graph G = (V, E), where V consists of componentslatches and functional elementsand E represents intercomponent connections. The algorithm verifies the proper timing of a circuit in worstcase O(V/E) time and O(V + E) space. Our analysis decouples the problem of generating timing constraints from the problem of efficiently checking them. We show how various base step functions can be used to provide sufficient conditions for a circuit to operate properly, and we provide a new base step function which is less pessimistic than those used in previous timing verifiers, yet correctly handles timing constraints that are cyclic or extend across the boundaries of multiple clock phases or cycles. The base step function is used to derive a computational expansion of the circuit from which a collection of simple linear constraints are derived. These constraints can be efficiently checked using standard graph algorithms. VLSI systems, Levelclocking, Timing constraints, Timing analysis, Timing verification, Computational expansions, Deltaconstraints, Formal modeling, Graph algorithm applications, Algorithmic techniques
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Related Identities
 Cormen, Thomas H. Author
 Rivest, Ronald L.
 Massachusetts Institute of Technology Microsystems Research Center
 Cazin, Xavier
 Chrétienne, Philippe
 Rivest, Ronald
 Stein, Clifford (1965....)
 Saxe, James B.
 Massachusetts Institute of Technology Laboratory for Computer Science
 Leighton, Frank Thomson Author
Useful Links
Associated Subjects
Algorithms Combinatorial optimization Computer algorithms Computer architecture Computer programming Data structures (Computer science) Electronic circuits Electronic digital computersCircuits Graph theory Graph theoryData processing Integrated circuits Integrated circuitsDesign and construction Integrated circuitsLarge scale integration Integrated circuitsVery large scale integration Linear programmingData processing MicrocomputersBuses Multiprocessors Parallel processing (Electronic computers) Permutations Queuing theory Rectangles Supercomputers Synchronization Systolic array circuits Trees (Graph theory)Data processing