Leiserson, Charles Eric
Overview
Works:  79 works in 369 publications in 7 languages and 3,010 library holdings 

Genres:  Conference papers and proceedings 
Roles:  Author, Editor, Other 
Classifications:  QA76.6, 005.1 
Publication Timeline
.
Most widely held works by
Charles Eric Leiserson
Introduction to algorithms by
Thomas H Cormen(
Book
)
120 editions published between 1989 and 2017 in 6 languages and held by 1,940 WorldCat member libraries worldwide
This edition has been revised and updated throughout. It includes some new chapters. It features improved treatment of dynamic programming and greedy algorithms as well as a new notion of edgebased flow in the material on flow networks.[book cover]
120 editions published between 1989 and 2017 in 6 languages and held by 1,940 WorldCat member libraries worldwide
This edition has been revised and updated throughout. It includes some new chapters. It features improved treatment of dynamic programming and greedy algorithms as well as a new notion of edgebased flow in the material on flow networks.[book cover]
Areaefficient VLSI computation by
Charles Eric Leiserson(
Book
)
21 editions published between 1981 and 1987 in English and Undetermined and held by 311 WorldCat member libraries worldwide
The two parts of this thesis address two measures of efficiency. Part 1 analyzes systolic systems which marry the ideas of pipelining and multiprocessing in a single framework of design. Part II looks at the layout of their communication paths. Although the two parts fit together, it should be understood that the ideas in each stand alone. The results of Part I can be applied to systems which are not systolic, and even systems which are not assembled on integrated circuits. The layout results of Part II can be applied to more general communication structures than graphs of systolic systems, and the ideas for representing layouts can be used in other routing algorithms
21 editions published between 1981 and 1987 in English and Undetermined and held by 311 WorldCat member libraries worldwide
The two parts of this thesis address two measures of efficiency. Part 1 analyzes systolic systems which marry the ideas of pipelining and multiprocessing in a single framework of design. Part II looks at the layout of their communication paths. Although the two parts fit together, it should be understood that the ideas in each stand alone. The results of Part I can be applied to systems which are not systolic, and even systems which are not assembled on integrated circuits. The layout results of Part II can be applied to more general communication structures than graphs of systolic systems, and the ideas for representing layouts can be used in other routing algorithms
Advanced research in VLSI : proceedings of the fourth MIT conference, April 79, 1986 by
1986, Cambridge, Mass.> Conference on Advanced Research in VLSI. <4(
Book
)
12 editions published in 1986 in 3 languages and held by 225 WorldCat member libraries worldwide
12 editions published in 1986 in 3 languages and held by 225 WorldCat member libraries worldwide
Introduction à l'algorithmique by
Thomas H Cormen(
Book
)
7 editions published between 1994 and 2000 in French and held by 154 WorldCat member libraries worldwide
7 editions published between 1994 and 2000 in French and held by 154 WorldCat member libraries worldwide
Retiming synchronous circuitry by
Charles Eric Leiserson(
Book
)
12 editions published between 1986 and 1988 in English and Undetermined and held by 28 WorldCat member libraries worldwide
This paper describes a circuit transformation called retiming in which registers are added at some points in a circuit and removed from others in such a way that he functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex set V is a collection of combinational logic elements and the edge set E is the set of interconnections, each of which may pass through zero or more registers. We give an algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomialtime solvable. This result yields a polynomialtime optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a characterization of optimal retiming based on an efficiently solvable mixedinteger linear programming problem. Keywords include: Digital circuitry, Graph theory, Linear programming, Network flow, Optimization, Pipelining, Propagation delay, Retiming, Synchronous circuitry, and Systolic circuits. (RH)
12 editions published between 1986 and 1988 in English and Undetermined and held by 28 WorldCat member libraries worldwide
This paper describes a circuit transformation called retiming in which registers are added at some points in a circuit and removed from others in such a way that he functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex set V is a collection of combinational logic elements and the edge set E is the set of interconnections, each of which may pass through zero or more registers. We give an algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomialtime solvable. This result yields a polynomialtime optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a characterization of optimal retiming based on an efficiently solvable mixedinteger linear programming problem. Keywords include: Digital circuitry, Graph theory, Linear programming, Network flow, Optimization, Pipelining, Propagation delay, Retiming, Synchronous circuitry, and Systolic circuits. (RH)
Wprowadzenie do algorytmów by
Thomas H Cormen(
Book
)
9 editions published between 1997 and 2017 in Polish and held by 13 WorldCat member libraries worldwide
9 editions published between 1997 and 2017 in Polish and held by 13 WorldCat member libraries worldwide
A mixedinteger linear programming problem which is efficiently solvable by
Charles Eric Leiserson(
Book
)
7 editions published between 1984 and 1987 in English and held by 11 WorldCat member libraries worldwide
Much research has centered on the problem of finding shortest paths in graphs. It is well known that there is a direct correspondence between the single source shortestpaths problem and the following simple linear programming problems: Let S be a set of linear inequalities of the form x sub j  x sub i <or = (a sub ij, where the x sub i are unknowns and the a sub ij are given real constants. Determine a set of values for the x sub i such that the inequalities in S are satisfied, or determine that no such values exist. This paper considers the mixedinteger linear programming variant of this problem in which some (but not necessarily all) of the x sub i are required to be integers. The problem arises in the context of synchronous circuit optimization but it has applications to PERT scheduling and VLSI layout compaction as well. Keywords: Algorithms, Combinatorial optimization
7 editions published between 1984 and 1987 in English and held by 11 WorldCat member libraries worldwide
Much research has centered on the problem of finding shortest paths in graphs. It is well known that there is a direct correspondence between the single source shortestpaths problem and the following simple linear programming problems: Let S be a set of linear inequalities of the form x sub j  x sub i <or = (a sub ij, where the x sub i are unknowns and the a sub ij are given real constants. Determine a set of values for the x sub i such that the inequalities in S are satisfied, or determine that no such values exist. This paper considers the mixedinteger linear programming variant of this problem in which some (but not necessarily all) of the x sub i are required to be integers. The problem arises in the context of synchronous circuit optimization but it has applications to PERT scheduling and VLSI layout compaction as well. Keywords: Algorithms, Combinatorial optimization
Waferscale integration of systolic arrays by
Frank Thomson Leighton(
Book
)
6 editions published between 1983 and 1985 in English and held by 11 WorldCat member libraries worldwide
VLSI technologies are fast developing waferscale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind waferscale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating waferscale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NPcomplete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, faulttolerant systems and planar geometry
6 editions published between 1983 and 1985 in English and held by 11 WorldCat member libraries worldwide
VLSI technologies are fast developing waferscale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind waferscale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating waferscale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NPcomplete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, faulttolerant systems and planar geometry
The organization of permutation architectures with bussed interconnections by
Joe Kilian(
Book
)
5 editions published between 1987 and 1989 in English and held by 9 WorldCat member libraries worldwide
This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to pointtopoint interconnections, we show the number of pins per chip can often be reduced. We also consider uniform permutation architectures that realize permutations in several clock ticks, instead of one, and show that further savings in the number of pins per chip can be obtained. Keywords: Barrel shifter, Bussed interconnections, Cyclic shifter, Difference cover, Difference set, Group theory, Permutation, Permutation architecture, Projective plane, Specialpurpose architecture, Uniform architecture
5 editions published between 1987 and 1989 in English and held by 9 WorldCat member libraries worldwide
This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to pointtopoint interconnections, we show the number of pins per chip can often be reduced. We also consider uniform permutation architectures that realize permutations in several clock ticks, instead of one, and show that further savings in the number of pins per chip can be obtained. Keywords: Barrel shifter, Bussed interconnections, Cyclic shifter, Difference cover, Difference set, Group theory, Permutation, Permutation architecture, Projective plane, Specialpurpose architecture, Uniform architecture
Areaefficient graph layouts (for VLSI) by
Charles Eric Leiserson(
Book
)
4 editions published between 1980 and 1981 in English and held by 8 WorldCat member libraries worldwide
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph. We give an algorithm that produces VLSI layouts for classes of graphs that have good separator theorems. We show in particular that any planar graph of n vertices has an O(n lgsquare(n)) area layout and that any tree of n vertices can be laid out in linear area. The algorithm maintains a sparse representation for layouts that is based on the wellknown UNIONFIND data structure, and as a result, the running time devoted to management of this representation is nearly linear. (Author)
4 editions published between 1980 and 1981 in English and held by 8 WorldCat member libraries worldwide
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph. We give an algorithm that produces VLSI layouts for classes of graphs that have good separator theorems. We show in particular that any planar graph of n vertices has an O(n lgsquare(n)) area layout and that any tree of n vertices can be laid out in linear area. The algorithm maintains a sparse representation for layouts that is based on the wellknown UNIONFIND data structure, and as a result, the running time devoted to management of this representation is nearly linear. (Author)
VLSI theory and parallel supercomputing by
Charles Eric Leiserson(
Book
)
3 editions published in 1989 in English and held by 8 WorldCat member libraries worldwide
3 editions published in 1989 in English and held by 8 WorldCat member libraries worldwide
Systolic priority queues by
Charles Eric Leiserson(
Book
)
3 editions published in 1979 in English and held by 8 WorldCat member libraries worldwide
Advances in microelectronics have made the realization of smart data structures a practical reality. VLSI gives us the capability of building logicinmemory hardware that will drastically change how things are computed. Models of computation based solely on the Von Neumann architecture will be insufficient to evaluate algorithms. Multiprocessor devices like the systolic multiqueue will introduce new cost functions to the sequential algorithm designer. But much work must be done to define and examine the models of parallel computation that lie between the mathematical world of computable functions and the physical world of space and time
3 editions published in 1979 in English and held by 8 WorldCat member libraries worldwide
Advances in microelectronics have made the realization of smart data structures a practical reality. VLSI gives us the capability of building logicinmemory hardware that will drastically change how things are computed. Models of computation based solely on the Von Neumann architecture will be insufficient to evaluate algorithms. Multiprocessor devices like the systolic multiqueue will introduce new cost functions to the sequential algorithm designer. But much work must be done to define and examine the models of parallel computation that lie between the mathematical world of computable functions and the physical world of space and time
Randomized routing on fattrees by
R. I Greenberg(
Book
)
5 editions published between 1985 and 1986 in English and held by 8 WorldCat member libraries worldwide
Fattrees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fattree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. This document shows that if a set of messages has load factor lambda on a fattree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1O(1/n). The best previous bound was O(lambda lg n) for the offline problem where switch settings can be determined in advance. In a VLSIlike model where hardware cost is equated with physical volume, the routing algorithm demonstrates that fattrees are universal routing networks in the sense that any routing network can be efficiently simulated by a fattree of comparable hardware cost
5 editions published between 1985 and 1986 in English and held by 8 WorldCat member libraries worldwide
Fattrees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fattree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. This document shows that if a set of messages has load factor lambda on a fattree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1O(1/n). The best previous bound was O(lambda lg n) for the offline problem where switch settings can be determined in advance. In a VLSIlike model where hardware cost is equated with physical volume, the routing algorithm demonstrates that fattrees are universal routing networks in the sense that any routing network can be efficiently simulated by a fattree of comparable hardware cost
Theory of parallel and VLSI computation : lecture notes [for] 18.435/6.848 Fall 1987 by
Tom Leighton(
Book
)
6 editions published between 1988 and 1992 in English and held by 7 WorldCat member libraries worldwide
6 editions published between 1988 and 1992 in English and held by 7 WorldCat member libraries worldwide
Optimixing Synchronous Systems(
Book
)
1 edition published in 1982 in English and held by 2 WorldCat member libraries worldwide
The complexity of integratedcircuit chips produced today makes it feasible to build inexpensive, specialpurpose subsystems that rapidly solve sophisticated problems on behalf of a generalpurpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more timeefficient, systolic implementations by removing combinational rippling. The problem of determining the optimized system can be reduced to the graphtheoretic singledestinationshortestpaths problem. More importantly from an engineering standpoint, however, the kinds of rippling that can be removed from a circuit at essentially no cost can be easily characterized. For example, if the only global communication in a system is broadcasting from the host computer, the broadcast can always be replaced by local communication. (Author)
1 edition published in 1982 in English and held by 2 WorldCat member libraries worldwide
The complexity of integratedcircuit chips produced today makes it feasible to build inexpensive, specialpurpose subsystems that rapidly solve sophisticated problems on behalf of a generalpurpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more timeefficient, systolic implementations by removing combinational rippling. The problem of determining the optimized system can be reduced to the graphtheoretic singledestinationshortestpaths problem. More importantly from an engineering standpoint, however, the kinds of rippling that can be removed from a circuit at essentially no cost can be easily characterized. For example, if the only global communication in a system is broadcasting from the host computer, the broadcast can always be replaced by local communication. (Author)
SPAA, 95: 7th Symposium on Parallel Algorithms and Architectures by
Charles Eric Leiserson(
Book
)
2 editions published in 1995 in English and held by 1 WorldCat member library worldwide
2 editions published in 1995 in English and held by 1 WorldCat member library worldwide
SPAA, 97: 9th Annual ACM Symposium on Parallel Algoriths and Architectures by
Charles Eric Leiserson(
Book
)
2 editions published in 1997 in English and held by 1 WorldCat member library worldwide
2 editions published in 1997 in English and held by 1 WorldCat member library worldwide
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Related Identities
 Rivest, Ronald L. Author
 Cormen, Thomas H. Author
 Stein, Clifford 1965
 Massachusetts Institute of Technology Microsystems Research Center
 Cazin, Xavier
 Chrétienne, Philippe
 Saxe, James B.
 Massachusetts Institute of Technology Laboratory for Computer Science
 ACM Digital Library
 MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
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Associated Subjects
Algorithms Combinatorial optimization Computer algorithms Computer architecture Computer programming Computer programmingAbility testing Data structures (Computer science) Electronic circuits Electronic digital computersCircuits Graph theory Graph theoryData processing Integrated circuitsDesign and construction Integrated circuitsLarge scale integration Integrated circuitsVery large scale integration Linear programmingData processing MicrocomputersBuses Microelectronics Multiprocessors Parallel processing (Electronic computers) Permutations Queuing theory Supercomputers Synchronization Trees (Graph theory)Data processing
Alternative Names
Charles E. Leiserson Amerikaans informaticus
Charles E. Leiserson amerikansk ingeniør og informatikar
Charles E. Leiserson amerikansk ingeniør og informatiker
Charles E. Leiserson amerikansk ingenjör och datavetare
Charles E. Leiserson informaticien américain
Charles E. Leiserson USamerikanischer Forscher
Charles Eric Leiserson
Leiserson, C.
Leiserson, C. E.
Leiserson, Charles
Leiserson, Charles E.
Лейзерсон, Ч.
Лейзерсон, Чарльз Эрик
Чарльз Эрик Лейзерсон
ליזרסון, צ'רלס א.
چارلز ای لیزرسان دانشمند علوم کامپیوتر و مهندس آمریکایی
ライザーソン, C.
ライザーソン, C. E.
查尔斯·雷瑟尔森
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