University of Michigan Department of Electrical Engineering and Computer Science
Most widely held works about University of Michigan
Most widely held works by University of Michigan
Multichannel multiplexed intracortical recording arrays ( Book )
1 edition published in 1985 in English and held by 89 WorldCat member libraries worldwide
Ninth Great Lakes Symposium on VLSI : proceedings : Ypsilanti Marriott at Eagle Court, Ypsilanti, Michigan, March 4-6, 1999 by Great Lakes Symposium on VLSI ( Book )
3 editions published between 1999 and 2002 in English and held by 64 WorldCat member libraries worldwide
Digest of papers by International Symposium on Fault-Tolerant Computing ( Book )
3 editions published in 1985 in English and held by 47 WorldCat member libraries worldwide
Proceedings, Ninth Great Lakes Symposium on VLSI March 4-6, 1999, Ypsilanti Marriott at Eagle Court, Ypsilanti, Michigan by Great Lakes Symposium on VLSI ( )
1 edition published in 2002 in English and held by 8 WorldCat member libraries worldwide
Modeling concept acquisition in the context of a unified theory of cognition by Craig S Miller ( Book )
2 editions published in 1993 in English and held by 7 WorldCat member libraries worldwide
Abstract: "This dissertation presents a process model of human learning in the context of supervised concept acquisition. I describe SCA (Symbolic Concept Acquisition), a computational model that acquires and retrieves category prediction rules. SCA is a fully symbolic approach that retrieves prediction rules searching from specific to general. From training examples, it acquires general rules but then incrementally learns more specific ones. SCA's plausibility as a model of human learning is motivated by its functionality, its ability to replicate human behavior and its constitution within a unified theory of cognition. Functionally, SCA meets task demands by performing incremental, noise-tolerant learning within real time
Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors by Tse-Yu Yeh ( Book )
2 editions published in 1993 in English and held by 6 WorldCat member libraries worldwide
Abstract: "As the issue width and depth of pipelining of high performance superscalar processors increase, the importance of an effective instruction fetch mechanism becomes vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. In this thesis a new dynamic branch predictor (Two-Level Adaptive Branch Prediction) and a new instruction fetch mechanism suitable for superscalar processors are proposed to reduce the branch execution penalty in instruction fetch. The branch predictor uses two levels of branch history information to make predictions: the history of the last k branches encountered, and the branch behavior for the last s occurrences of the specific pattern of these k branches. Its nine variations are identified according to how finely the history information is gathered. The cost- effectiveness of the variations is compared. Simulation results show that the average misprediction rate for the Two-Level Adaptive branch predictor with a reasonable implementation cost is 3% over nine programs in the SPEC89 benchmark suite, while other known schemes achieve at least 5.6% average misprediction rate. The branch predictor is integrated into an instruction fetch mechanism that is able to fetch multiple instructions each cycle and change instruction flow without incurring any pipeline bubbles. Compared with designs which use other branch predictors, the proposed design significantly reduces the branch execution penalty."
Materials of the tutorial course EECS 500 communication networks ( )
4 editions published between 1996 and 1998 in English and held by 6 WorldCat member libraries worldwide
Fault-tolerant computing symposium : FTCS 15 : digest of papers [presented at] the Fifteenth Annual International Symposium on Fault-Tolerant Computing, June 19-21, 1985, Horace H. Rackham Building The University of Michigan, Ann Arbor, Michigan, USA. by International Symposium on Fault-Tolerant Computing ( Book )
1 edition published in 1985 in English and held by 6 WorldCat member libraries worldwide
Materials of the tutorial lectures in systems sciences EECS 500 ( )
4 editions published between 2001 and 2002 in English and held by 6 WorldCat member libraries worldwide
Instructable autonomous agents CSE-TR-193-94 by Scott Bradley Huffman ( Book )
2 editions published in 1994 in English and held by 6 WorldCat member libraries worldwide
Abstract: "In contrast to current intelligent systems, which must be laboriously programmed for each task they are meant to perform, instructable agents can be taught new tasks and associated knowledge. This thesis presents a general theory of learning from tutorial instruction and its use to produce an instructable agent. Tutorial instruction is a particularly powerful form of instruction, because it allows the instructor to communicate whatever kind of knowledge a student needs at whatever point it is needed. To exploit this broad flexibility, however, a tutorable agent must support a full range of interaction with its instructor to learn a full range of knowledge. Thus, unlike most machine learning tasks, which target deep learning of a single kind of knowledge from a single kind of input, tutorability requires a breadth of learning from a broad range of instructional interactions. The theory of learning from tutorial instruction presented here has two parts. First, a computational model of an intelligent agent, the problem space computational model, indicates the types of knowledge that determine an agent's performance, and thus, that should be acquirable via instruction. Second, a learning technique, called situated explanation, specifies how the agent learns general knowledge from instruction. The theory is embodied by an implemented agent, Instructo-Soar, built within the Soar architecture. Instructo-Soar is able to learn hierarchies of completely new tasks, to extend task knowledge to apply in new situations, and in fact to acquire every type of knowledge it uses during task performance -- control knowledge, knowledge of operator's effects, state inferences, etc. -- from interactive natural language instructions. This variety of learning occurs by applying the situated explanation technique to a variety of instructional interactions involving a variety of types of instructions (commands, statements, conditionals, etc.). By taking seriously the requirements of flexible tutorial instruction, Instructo-Soar demonstrates a breadth of interaction and learning capabilities that goes beyond previous instructable systems, such as learning apprentice systems. Instructo-Soar's techniques could form the basis for future 'instructable technologies' that come equipped with basic capabilities, and can be taught by novice users to perform any number of desired tasks."
Emergence of meta-level control in multi-tasking autonomous agents by Arie A Covrigaru ( Book )
2 editions published in 1992 in English and held by 5 WorldCat member libraries worldwide
Aggressive centralized and distributed scheduling of disk requests by Bruce L Worthington ( Book )
2 editions published in 1995 in English and held by 5 WorldCat member libraries worldwide
Abstract: "Disk request scheduling is a critical element of high- performance computer system design. Previous disk scheduling research is insufficient because it uses simplistic or outdated disk models, unrepresentative workloads, and inadequate performance metrics. This dissertation explores the disk scheduler design space and provides guidelines for computer system engineers. Host-based and disk-based centralized scheduling are compared with distributed scheduling, a new paradigm with cost, complexity, and performance advantages. In distributed scheduling, individual disk schedulers located at multiple points along the I/O path cooperate to make scheduling decisions. Scheduler implementations are evaluated using a detailed simulator containing validated models of state-of-the-art host systems, controllers, buses, and disk drives. The simulator is driven with extensive traces of real-world system and disk activity, and it reports system performance metrics (e.g., application run times) in addition to traditional disk subsystem metrics (e.g., mean request response times). It is shown that for the best system performance, scheduling algorithms must incorporate system-level information (e.g., request priorities). Scheduling algorithms that focus on reducing seek delays do not need extensive disk-specific information. Finally, algorithms must exploit a disk's on-board cache to achieve the lowest disk service times. Additional guidelines are provided for dealing with disk drive command queues, sequential disk request optimizations, and different on-board cache configurations."
Multi-configuration simulation algorithms for the evaluation of computer architecture designs by Rabin Sugumar ( Book )
2 editions published in 1993 in English and held by 5 WorldCat member libraries worldwide
Abstract: "In computer architecture design, a number of candidate design are simulated on representative workloads, and the most satisfactory design in terms of cost and performance is chosen. This simulation process is time-consuming, especially memory hierarchy simulation, and is a bottleneck in architectural design. In this thesis the multi-configuration simulation approach is adopted for speeding up the simulation process. This approach is based on the observation that the behavior of adjacent design configurations is largely similar, and that the similarity may be exploited to reduce simulation work; significant reductions in simulation time are obtained by a synergistic simulation of many design configurations. A suite of multi-configuration simulation algorithms is developed for memory hierarchy simulation. The suite includes 1. An algorithm for set-associative cache simulation based on a new data structure (the generalized binomial tree) which runs about two times faster than earlier algorithms. 2. An algorithm for direct mapped cache simulation based on a novel tag inclusion property which also gives a factor of two improvement over an earlier algorithm. 3. An innovative limited lookahead algorithm with stack repair for simulating the OPT replacement strategy in caches. 4. Novel multi-configuration simulation algorithms for write-buffers. A simulation package, Cheetah, based on these algorithms has been developed and used in the following modeling and optimization studies. First, a new model, the OPT model, is introduced for classifying cache misses. Unlike earlier models, the OPT model accounts for misses resulting from sub-optimal replacement policies used in practical caches. Experimental characterizations based on the OPT model of the cache misses occurring in the SPEC benchmarks are then presented. The results demonstrate that the replacement policy contributes to a significant fraction of cache misses. Second, the hit-miss and reuse behavior of individual load/store instructions of the SPEC benchmarks are profiled. The profiles show that a small number of instructions contribute to a large percentage of the misses. By scheduling the instructions that miss to hide latency, a factor of three improvement is demonstrated for loop-dominated code. By partially controlling cache replacement using the profile information on data reuse up to a 20% reduction in miss ratio is demonstrated."
Mapping the boundary between continuous and discontinuous permafrost in Alaska by A. W England ( Book )
1 edition published in 1995 in English and held by 5 WorldCat member libraries worldwide
Goal-directed performance tuning for scientific applications by Tien-Pao Shih ( Book )
2 editions published in 1996 in English and held by 5 WorldCat member libraries worldwide
Abstract: "Performance tuning, as carried out by compiler designers and application programmers to close the performance gap between the achievable peak and delivered performance, becomes increasingly important and challenging as the microprocessor speeds and system sizes increase. However, although performance tuning on scientific codes usually deals with relatively small program regions, it is not generally known how to establish a reasonable performance objective and how to efficiently achieve this objective. We suggest a goal-directed approach and develop such an approach for each of three major system performance components: central processor unit (CPU) computation, memory accessing, and communication. For the CPU, we suggest using a machine-application performance model that characterizes workloads on four key function units (memory, floating-point, issue, and a virtual 'dependence unit') to produce an upper bound performance objective, and derive a mechanism to approach this objective. A case study shows an average 1.79x speedup achieved by using this approach for the Livermore Fortran Kernels 1-12 running on the IBM RS/6000. For memory, as compulsory and capacity misses are relatively easy to characterize, we derive a method for building application-specific cache behavior models that report the number of misses for all three types of conflict misses: self, cross, and ping-pong. The method uses averaging concepts to determine the expected number of cache misses instead of attempting to count them exactly in each instance, which provides a more rapid, yet realistic assessment of expected cache behavior. For each type of conflict miss, we propose a reduction method that uses one or a combination of three techniques based on modifying or exploiting data layout: array padding, initial address adjustment, and access resequencing. A case study using a blocked matrix multiply program as an example shows that the model is within 11% of the simulation results, and that each type of conflict miss can be effectively reduced or completely eliminated. For communication in shared memory parallel systems, we derive an array grouping mechanism and related loop transformations to reduce communication caused by the problematic case of nonconsecutive references to shared arrays and prove several theorems that determine when and where to apply this technique. The experimental results show a 15% reduction in communication, a 40% reduction in data subcache misses, and an 18% reduction in maximum user time for a finite element application on a 56 processor KSR1 parallel computer."
Transistor level micro placement and routing for two-dimensional digital VLSI cell synthesis by Michael A Riepe ( Book )
2 editions published in 1999 in English and held by 5 WorldCat member libraries worldwide
A survey of some existing IVHS systems, their functionality, and how they are achieved by Aviel D Rubin ( Book )
1 edition published in 1991 in English and held by 5 WorldCat member libraries worldwide
Loop optimization techniques on multi-issue architectures by Dan Richard Kaiser ( Book )
2 editions published in 1995 in English and held by 5 WorldCat member libraries worldwide
Abstract: "This work examines the interaction of compiler scheduling techniques with processor features such as the instruction issue policy. Scheduling techniques designed to exploit instruction level parallelism are employed to schedule instructions for a set of multi-issue architectures. A compiler is developed which supports block scheduling, loop unrolling, and software pipelining for a range of target architectures. The compiler supports aggressive loop optimizations such as induction variable detection and strength reduction, and code hoisting. A set of machine configurations based on the MIPS R3000 ISA are simulated, allowing the performance of the combined compiler-processor to be studied. The Aurora III, a prototype superscalar processor, is used as a case study for the interaction of compiler scheduling techniques with processor architecture. Our results show that the scheduling technique chosen for the compiler has a significant impact on the overall system performance and can even change the rank ordering when comparing the performance of VLIW, DAE and superscalar architectures. Our results further show that, while significant, the performance effects of the instruction issue policy may not be as large as the effects of other processor features, which may be less costly to implement, such as 64 bit wide data paths or store buffers."
Modeling dual-task performance improvement : casting executive process knowledge acquisition as strategy refinement by Ronald Samuel Chong ( Book )
2 editions published in 1998 in English and held by 5 WorldCat member libraries worldwide
Abstract: "People demonstrate a remarkable ability to perform complex, multiple-task activities in spite of the limitations of our sensory, perceptual, cognitive, and motor systems. A prominent theory that addresses how multiple-tasks activities are performed is that of the executive process. Some of the functions of the executive process include enforcing task priorities and arbitrating access to limited resources. It has been shown that a time-sharing skill (or executive-process knowledge) is acquired during training on dual-task combinations. This dissertation presents the development of a computational, task-independent framework for modeling the acquisition of the knowledge acquired during training on dual-task combinations -- executive process knowledge. On a selected dual-task combination -- a continuous tracking task and a discrete two-choice reaction time task -- this framework, when given the declarative and procedural representation of the novice task, has produced an expert model whose performance is a good match to empirical reaction time and tracking error data for the task combination. There are three main contributions of this work. First is the development of EPIC-Soar, a symbolic hybrid architecture that possesses a psychologically-motivated learning mechanism and psychologically-plausible perception and motor systems. Second is the identification and classification of executive process knowledge and the taxonomies that result from this analysis. Third, is an acquisition framework which consists of: a novel data structure for representing task strategies; a task-independent procedure for resolving simultaneous access for motor resources and learning new knowledge that avoids such collisions in the future; a second task-independent learning procedure which refines the strategy data structure and creates new procedural knowledge for performing the task; and a collection of guidelines that regulate how and when promotions are applied."
Trace cache design for wide-issue superscalar processors by Sanjay Jeram Patel ( Book )
2 editions published in 1999 in English and held by 5 WorldCat member libraries worldwide
Abstract: "To maximize the performance of a wide-issue superscalar processor, the fetch mechanism must be capable of delivering at least the same instruction bandwidth as the execution mechanism is capable of consuming. Fetch mechanisms consisting of a simple instruction cache are limited by difficulty in fetching a branch and its taken target in a single cycle. Such fetch mechanisms will not suffice for processors capable of executing multiple basic blocks' worth of instructions. The Trace Cache is proposed to deal with lost fetch bandwidth due to branches. The trace cache is a structure which overcomes this partial fetch problem by storing logically contiguous instructions -- instructions which are adjacent in the instruction stream -- in physically contiguous storage. In this manner, the trace cache is able to deliver multiple non-contiguous blocks each cycle. This dissertation contains a description of the trace cache mechanism for a 16-wide issue processor, along with an evaluation of basic parameters of this mechanism, such as relative size and associativity. The main contributions of this dissertation are a series of trace cache enhancements which boost instruction fetch bandwidth by 34% and overall performance by 14% over an aggressive instruction cache. Also included is an analysis of two important performance limitations of the trace cache: branch resolution time and instruction duplication."
Alaska Artificial intelligence Association for Computing Machinery Business and education Cache memory Compilers (Computer programs) Computer-aided design Computer algorithms Computer architecture Computer multitasking Computer networks Computer science Computers--Study and teaching Digital communications Digital electronics Education--Curricula Electronic digital computers Engineers Fault-tolerant computing Frozen ground High performance computing Highway communications Industrial Technology Institute (Ann Arbor, Mich.) Information organization Information retrieval Integrated circuits--Very large scale integration Integrated circuits--Very large scale integration--Design and construction Knowledge acquisition (Expert systems) Leith, Emmett N Machine learning Michigan--Ann Arbor Nervous system Parallel processing (Electronic computers) Research Students--Social life and customs Telecommunication--Study and teaching (Higher) Thin-film circuits Universities and colleges--Faculty University of Michigan University of Michigan.--Center for Research on Integrated Manufacturing University of Michigan.--College of Engineering University of Michigan.--Department of Electrical and Computer Engineering University of Michigan.--Department of Electrical Engineering University of Michigan.--Department of Electrical Engineering and Computer Science University of Michigan.--Engineering Research Institute University of Michigan.--Institute of Science and Technology University of Michigan.--Radiation Laboratory Women Women college students World War (1914-1918)
University of Michigan Computer Science and Engineering Division Department of Electrical Engineering and Computer Science
University of Michigan. Dept. of Electrical Engineering and Computer Science