WorldCat Identities

Stanford University Computer Systems Laboratory

Overview
Works: 774 works in 943 publications in 1 language and 1,036 library holdings
Genres: Periodicals  Conference papers and proceedings  History 
Classifications: H61.25, 620
Publication Timeline
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Most widely held works by Stanford University
Sparse distributed memory prototype : principles of operation by Stanford University( Book )

2 editions published in 1988 in English and held by 77 WorldCat member libraries worldwide

Preprints by Stanford University( Book )

8 editions published between 1986 and 1988 in English and held by 11 WorldCat member libraries worldwide

Abstracts and viewgraphs : from the Twentieth Annual Meeting of the Stanford Computer Forum, February 10/11, 1988 by Stanford Computer Forum( Book )

3 editions published between 1988 and 1991 in English and held by 7 WorldCat member libraries worldwide

Technical report by Stanford University( )

in English and Undetermined and held by 6 WorldCat member libraries worldwide

Generalized graphical object editing by John Vlissides( Book )

2 editions published in 1990 in English and held by 6 WorldCat member libraries worldwide

Super-scalar processor design by Stanford University( Book )

2 editions published in 1989 in English and held by 6 WorldCat member libraries worldwide

Theory and practice by Stanford University( Book )

in English and held by 5 WorldCat member libraries worldwide

Preprint[s] by Stanford University( Book )

5 editions published between 1993 and 1996 in English and held by 5 WorldCat member libraries worldwide

Verifying concurrent prcesses [sic] using temporal logic by Brent T Hailpern( Book )

2 editions published between 1980 and 1983 in English and held by 5 WorldCat member libraries worldwide

Fred Terman, the father of Silicon Valley by C. E Tajnai( Book )

2 editions published in 1985 in English and held by 5 WorldCat member libraries worldwide

One-to-many interprocess communication in the V-system by David R Cheriton( Book )

1 edition published in 1984 in English and held by 5 WorldCat member libraries worldwide

Scan line access memories for high speed image rasterization by Stefan G Demetrescu( Book )

1 edition published in 1986 in English and held by 5 WorldCat member libraries worldwide

Simulation of busy tone multiple access modes in multihop packet radio networks by Fouad A Tobagi( Book )

1 edition published in 1982 in English and held by 4 WorldCat member libraries worldwide

In this study we examine via simulation, the performance of the ALOHA, CSMA, BTMA, and CDMA channel access schemes in multihop packet radio systems. The performance of CSMA, which is efficient in fully-connected environments, is shown to degrade significantly in the presence of hidden nodes. The BTMA protocol attempts to overcome the hidden node problem and to obtain efficient channel utilization in multihop environments by having nodes transmit a busy tone when they are busy receiving. In an example of a six node ring topology, we compare the performance of the CSMA and ALOHA schemes with four variants of BTMA. The highest throughput is achieved by II-BTMA and C-BTMA, which both significantly outperform the CSMA and ALOHA schemes. Our conclusion is that the improvement in bandwidth utilization achieved by BTMA in environments with hidden nodes, is expected to more than compensate for the cost of the busy tone channel. (Author)
Detecting bridging faults with stuck-at test sets by Stanford University( Book )

1 edition published in 1987 in English and held by 4 WorldCat member libraries worldwide

Simulations run on sample circuits show that extremely high detection of bridging faults is possible using modifications of psuedo-exhaustive test sets. Real chips often contain bridging faults, and this research shows that stuck-at test sets are not sufficient for detecting such faults. The modified pseudo-exhaustive test sets are easy to generate and require little, or no, fault simulation. Criteria have been found for identifying bridging faults unlikely to be detected by test sets. Techniques for increasing the bridging fault coverage of test sets without consuming excessive computer time are suggested. Keywords: Bridging faults, stuck-at faults, pseudo-exhaustive test, fault modeling, fault tolerant computing
Software-controlled caches in the VMP multiprocessor by David R Cheriton( Book )

1 edition published in 1986 in English and held by 4 WorldCat member libraries worldwide

VMP is an experimental multiprocessor that follows the familiar basic design of multiple processors, each with a cache, connected by a shared bus to global memory. Each processor has a synchronous, virtually addressed, single master connection to its cache, providing very high memory bandwidth. An unusually large cache page size and fast sequential memory copy hardware make it feasible for cache misses to be handled in software, analogously to the handling of virtual memory page faults. Hardware support for cache consistency is limited to a simple state machine that monitors the bus and interrupts the processor when a cache consistency action is required. In this paper, we show how the VMP design provides the high memory bandwidth required by modern high-performance processors with a minimum of hardware complexity and cost. We also describe simple solutions to the consistency problems associated with virtually addressed caches. Simulation results indicate that the design achieves good performance providing data contention is not excessive. (kr)
Taliesin : a distributed bulletin board system by Judy L Edighoffer( Book )

1 edition published in 1985 in English and held by 4 WorldCat member libraries worldwide

This paper describes a computer bulletin board facility intended to support replicated bulletin boards on a network that may frequently be in state of partition. The two major design issues covered are the choice of a name space and the choice of replication algorithms. The impact of the name space on communication costs is explained. A special purpose replication algorithm that provides high availability and response network partition is introduced
Unidraw : a framework for building domain-specific graphical editors by John Vlissides( Book )

2 editions published in 1989 in English and held by 4 WorldCat member libraries worldwide

Unidraw is a framework for creating object-oriented graphical editors in domains such as technical and artistic drawing, music composition, and CAD. The Unidraw architecture simplifies the construction of these editors by providing programming abstractions that are common across domains. Unidraw defines four basic abstractions: components encapsulate the appearance and semantics of objects in a domain, tools support direct manipulation of components, commands define operations on components and other objects, and external representations define the mapping between components and the file format generated by the editor. Unidraw also supports multiple views, graphical connectivity and confinement, and dataflow between components. This paper describes the Unidraw design, implementation issues, and three prototype domain-specific editors we have developed with Unidraw: a drawing editor, a user interface builder, and a schematic capture system. Experience indicates a substantial reduction in implementation time compared with existing tools
Logic design education at Stanford University by Stanford University( Book )

1 edition published in 1987 in English and held by 4 WorldCat member libraries worldwide

Exhaustive and pseudo-exhaustive testing by Stanford University( Book )

1 edition published in 1987 in English and held by 4 WorldCat member libraries worldwide

This chapter discusses an approach to test pattern generation for functional testing of combinational digital integrated circuits. The techniques to be presented apply all possible input patterns either to the entire circuit under test or to portions of the circuit under test. For some circuits, exhaustive testing is economically practical: all possible input combinations are applied to the entire circuit. An exhaustive test is a complete functional test and no assumptions about the internal structure of the circuit under test are required. When the number of inputs is so large that an exhaustive test is impractical, it is still possible to retain many of the advantages of exhaustive testing by using a pseudo-exhaustive test technique. Pseudo-exhaustive testing requires that some details of the internal circuit structure either be known or assumed. A disadvantage of exhaustive and pseudo-exhaustive testing is the size of the test sets: they can be substantially larger than minimum-length test sets. The major advantages of exhaustive and pseudo-exhaustive tests are the extremely high fault coverage, the generality of the fault model, and the absence of a requirement to do fault simulation. Another advantage of output function verification is the ease of generating the test set. Segmentation and determination of the corresponding test sets requires more computation. Keywords: Fault tolerant computing
Testable structures for CMOS VLSI circuits by Stanford University( Book )

1 edition published in 1987 in English and held by 4 WorldCat member libraries worldwide

 
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Alternative Names

controlled identityStanford University. Computer Science Department

controlled identityStanford University. Department of Electrical Engineering

Computer Systems Laboratory

Computer Systems Laboratory (Stanford University)

CSL

Stanford Computer Systems Laboratory

Stanford University. Computer Science Department. Computer Systems Laboratory

Stanford University Department of Computer Science Computer Systems Laboratory

Stanford University Department of Electrical Engineering Computer Systems Laboratory

Languages
English (40)