WorldCat Identities

Furber, Stephen B. (Stephen Bo) 1953-

Works: 37 works in 104 publications in 5 languages and 936 library holdings
Genres: Conference papers and proceedings  Exhibition catalogs 
Roles: Author, Editor
Publication Timeline
Most widely held works by Stephen B Furber
ARM system-on-chip architecture by Stephen B Furber( Book )

25 editions published between 2000 and 2002 in 3 languages and held by 269 WorldCat member libraries worldwide

The future of the computer and communications industries is converging on mobile information appliances- phones, PDAs, laptops and other devices. The ARM is at the heart of this trend, leading the way in system-on-chip (SoC) development and becoming the processor core of choice for many embedded applications. System-on-chip technology is changing the way we use computers, but it also sets designers the very challenging problem of getting a complex SoC design right first time. ARM System-on-Chip Architecture introduces the concepts and methodologies employed in designing a system-on-chip based around a microprocessor core, and in designing the core itself. Extensive illustrations, based on the ARM, give practical substance to the design principles set out in the book, reinforcing the reader's understanding of how and why SoCs and microprocessors are designed as they are
VLSI RISC architecture and organization by Stephen B Furber( Book )

11 editions published between 1989 and 1992 in English and Japanese and held by 204 WorldCat member libraries worldwide

Principles of asynchronous circuit design : a systems perspective by Jens Sparsø( Book )

10 editions published between 2001 and 2010 in English and held by 144 WorldCat member libraries worldwide

"Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. The objective in writing this book bas been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task."--Jacket
ARM system architecture by Stephen B Furber( Book )

9 editions published between 1996 and 1999 in English and held by 107 WorldCat member libraries worldwide

Asynchronous design methodologies : proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March-2 April, 1993 by Asynchronous Design Methodologies ; 31/03/1993-02/04/199 ; Manchester gb( Book )

7 editions published in 1993 in English and held by 73 WorldCat member libraries worldwide

ARM SoC ti xi jie gou by bo Fu( Book )

3 editions published between 2002 and 2005 in Chinese and held by 31 WorldCat member libraries worldwide

Algorithms and Hardware for Reasoning in Factor Graphs Stephen Furber ; Klaus Diepold by Indar Sugiarto( )

1 edition published in 2015 in English and held by 16 WorldCat member libraries worldwide

ARM purosessa : 32bitto RISC no shisutemu ākitekucha by Stephen B Furber( Book )

6 editions published between 1999 and 2001 in Japanese and held by 6 WorldCat member libraries worldwide

Design, analysis and implementation of a self-timed duplex communication system by Alex Yakovlev( Book )

2 editions published between 2002 and 2003 in English and held by 3 WorldCat member libraries worldwide

The imitation game by Manchester Art Gallery( Book )

1 edition published in 2016 in English and held by 2 WorldCat member libraries worldwide

Beyond Moore's law : papers of a discussion meeting( )

1 edition published in 2014 in English and held by 2 WorldCat member libraries worldwide

Managing a real-time massively-parallel neural architecture by James Cameron Patterson( Book )

2 editions published in 2012 in Undetermined and English and held by 2 WorldCat member libraries worldwide

A human brain has billions of processing elements operating simultaneously; the only practical way to model this computationally is with a massively-parallel computer. A computer on such a significant scale requires hundreds of thousands of interconnected processing elements, a complex environment which requires many levels of monitoring, management and control. Management begins from the moment power is applied and continues whilst the application software loads, executes, and the results are downloaded. This is the story of the research and development of a framework of scalable management tools that support SpiNNaker, a novel computing architecture designed to model spiking neural networks of biologically-significant sizes. This management framework provides solutions from the most fundamental set of power-on self-tests, through to complex, real-time monitoring of the health of the hardware and the software during simulation. The framework devised uses standard tools where appropriate, covering hardware up / down events and capacity information, through to bespoke software developed to provide real-time insight to neural network software operation across multiple levels of abstraction. With this layered management approach, users (or automated agents) have access to results dynamically and are able to make informed decisions on required actions in real-time
Error control with binary cyclic codes by Martin-Thomas Grymel( )

1 edition published in 2013 in English and held by 1 WorldCat member library worldwide

Error-control codes provide a mechanism to increase the reliability of digital data being processed, transmitted, or stored under noisy conditions. Cyclic codes constitute an important class of error-control code, offering powerful error detection and correction capabilities. They can easily be generated and verified in hardware, which makes them particularly well suited to the practical use as error detecting codes. A cyclic code is based on a generator polynomial which determines its properties including the specific error detection strength. The optimal choice of polynomial depends on many factors that may be influenced by the underlying application. It is therefore advantageous to employ programmable cyclic code hardware that allows a flexible choice of polynomial to be applied to different requirements. A novel method is presented in this thesis to realise programmable cyclic code circuits that are fast, energy-efficient and minimise implementation resources. It can be shown that the correction of a single-bit error on the basis of a cyclic code is equivalent to the solution of an instance of the discrete logarithm problem. A new approach is proposed for computing discrete logarithms; this leads to a generic deterministic algorithm for analysed group orders that equal Mersenne numbers with an exponent of a power of two. The algorithm exhibits a worst-case runtime in the order of the square root of the group order and constant space requirements. This thesis establishes new relationships for finite fields that are represented as the polynomial ring over the binary field modulo a primitive polynomial. With a subset of these properties, a novel approach is developed for the solution of the discrete logarithm in the multiplicative groups of these fields. This leads to a deterministic algorithm for small group orders that has linear space and linearithmic time requirements in the degree of defining polynomial, enabling an efficient correction of single-bit errors based on the corresponding cyclic codes
Quality-of-Service (QoS) for asynchronous On-Chip Networks by Tomaz Felicijan( Book )

1 edition published in 2004 in English and held by 1 WorldCat member library worldwide

Exploiting concurrency in a general purpose one-instruction computer architecture by Christopher Daniel Emmons( Book )

1 edition published in 2010 in Undetermined and held by 1 WorldCat member library worldwide

Four-phase micropipeline latch control circuits by Stephen B Furber( )

1 edition published in 1996 in English and held by 1 WorldCat member library worldwide

Injuries to ambulance officers caused by patient handling tasks by Stephen B Furber( Book )

1 edition published in 1997 in English and held by 1 WorldCat member library worldwide

The relentless march of the microchip by Stephen B Furber( Visual )

1 edition published in 2010 in English and held by 1 WorldCat member library worldwide

The first sixty years of computing have seen spectacular progress in the technology, driven for the last forty years by Moore's Law which, though initially an observation, has become a self-fulfilling prophecy and a board-room planning tool. Ever shrinking transistor dimensions have yielded increasingly complex and cost-effective microchips, a win-win scenario that has driven the explosion in the use of digital electronics and enabled computers to be embedded into a vast range of high-volume products. However, there are limits to how small a transistor can be made, and one can no longer assume that smaller circuits will go faster, or be more power-efficient. As we approach atomic limits device variability is beginning to hurt, and the cost of microchip design is spiralling upwards. On the desktop, technology changes are driving a trend away from high-speed uniprocessors towards multi-core, and soon many-core, processors, despite the fact that general-purpose parallel programming remains one of the great unsolved problems of computer science. If the cost-effectiveness of microchip technology is to continue to improve there are major challenges ahead involving understanding how to build reliable systems on increasingly unreliable technology and how to exploit parallelism increasingly effectively, not only to improve performance, but also to mask the consequences of component failure. Biological systems demonstrate many of the properties we aspire to incorporate into engineered technology, and therefore are a possible source of ideas to incorporate into future novel computation systems. This lecture discusses current research at Manchester into the development of the 'Brain Box' computer, which is a contribution to the computing Grand Challenge of 'Understanding the Architecture of Brain and Mind', and will provide a platform for the investigation of these important issues that face the microchip industry in the near future
Informatica sin relojes : logica asincrona de bajo consumo by Stephen B Furber( )

1 edition published in 1995 in Spanish and held by 1 WorldCat member library worldwide

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  Kids General Special  
Audience level: 0.69 (from 0.49 for Four-phase ... to 0.94 for Algorithms ...)

ARM system-on-chip architecture
Alternative Names
Furber, S.

Furber, S. 1953-

Furber, S. (Stephe), 1953-

Furber, S. (Stephen), 1953-

Furber, Stephen 1953-

Furber, Stephen B.

Furber, Stephen Bo 1953-

Furber, Steve.

Furber, Steve 1953-

Furber, Steve B.

Stephen Furber

Steve Furber britischer Informatiker

Steve Furber British computer scientist

Steve Furber Brits informaticus

Steve Furber informaticien britannique

Steve Furber informático teórico del Reino Unido

Фербер, Стивен

استیو فوربر

후버, 스테이브

VLSI RISC architecture and organizationPrinciples of asynchronous circuit design : a systems perspectiveARM system architecture