WorldCat Identities

Augustin, Larry M. 1962-

Overview
Works: 6 works in 22 publications in 1 language and 434 library holdings
Genres: Documentary films  Nonfiction films 
Roles: Author, Other
Publication Timeline
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Most widely held works by Larry M Augustin
Revolution OS by J. T. S Moore( Visual )

6 editions published between 2001 and 2003 in English and held by 212 WorldCat member libraries worldwide

Revolution OS depicts the inside story of the hackers and computer programmers who rebelled against Microsoft to create the Linux operating system
Hardware design and simulation in VAL/VHDL by Larry M Augustin( Book )

11 editions published between 1990 and 1991 in English and held by 157 WorldCat member libraries worldwide

The VHSIC Hardware Description Language (VHDL) provides a standard machine processable notation for describing hardware. VHDL is the result of a collaborative effort between IBM, Intermetrics, and Texas Instruments; sponsored by the Very High Speed Integrated Cir­ cuits (VHSIC) program office of the Department of Defense, beginning in 1981. Today it is an IEEE standard (1076-1987), and several simulators and other automated support tools for it are available commercially. By providing a standard notation for describing hardware, especially in the early stages of the hardware design process, VHDL is expected to reduce both the time lag and the cost involved in building new systems and upgrading existing ones. VHDL is the result of an evolutionary approach to language devel­ opment starting with high level hardware description languages existing in 1981. It has a decidedly programming language flavor, resulting both from the orientation of hardware languages of that time, and from a ma­ jor requirement that VHDL use Ada constructs wherever appropriate. During the 1980's there has been an increasing current of research into high level specification languages for systems, particularly in the software area, and new methods of utilizing specifications in systems de­ velopment. This activity is worldwide and includes, for example, object­ oriented design, various rigorous development methods, mathematical verification, and synthesis from high level specifications. VAL (VHDL Annotation Language) is a simple further step in the evolution of hardware description languages in the direction of applying new methods that have developed since VHDL was designed
Formal verification of VAL/VHDL using waveform albebra by Larry M Augustin( )

1 edition published in 1994 in English and held by 1 WorldCat member library worldwide

VAL to VHDL transformer: an implementation guide by Stanford University( Book )

2 editions published in 1989 in English and held by 1 WorldCat member library worldwide

This report presents one implementation of the VAL semantics. It is based on a transformation from VAL annotated VHDL to self-checking VHDL that is equivalent to the original source from the simulation semantics standpoint
Specification and analysis of system architecture using Rapide by Stanford University( Book )

1 edition published in 1994 in English and held by 1 WorldCat member library worldwide

Sparse distributed memory is a generalized random-access memory (RAM) for long (e.g., 1,000 bit) binary words. Such words can be written into and read from the memory, and they can also be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original write address but also by giving one close to it as measured by the Hamming distance between addresses
An Overview of VAL by Larry M Augustin( Book )

1 edition published in 1988 in English and held by 1 WorldCat member library worldwide

VAL (VHDL Annotation Language) provides a small number of new language constructs to annotate VHDL hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. Annotations are expressed as parallel processes that accept streams of input signals and generate constraints on output streams. VAL views signals as streams of values ordered by time. Generalized timing expressions allow the designer to refer to relative points on a stream. No concept of preemptive delayed assignment or inertial delay are needed when referring to different relative points in time on a stream. The VAL abstract state model permits abstract data types to be used in specifying history dependent device behavior. Annotations placed inside a VHDL architecture define detailed correspondences between the behavior specification and architecture. The result is a simple but expressive language extension of VHDL with possible applications to automatic checking of VHDL simulations, hierarchical design, and automatic verification of hardware designs in VHDL
 
Audience Level
0
Audience Level
1
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Audience level: 0.44 (from 0.27 for Revolution ... to 0.87 for VAL to VHD ...)

Hardware design and simulation in VAL/VHDL
Alternative Names
Larry Augustin Amerikaans ingenieur

Larry Augustin US-amerikanischer Ingenieur

Ларри Огустен

لاري أوغستين

拉里·奥古斯丁

Languages
English (22)

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