WorldCat Identities

Leroy, Xavier 1968-

Overview
Works: 14 works in 50 publications in 2 languages and 579 library holdings
Genres: Conference papers and proceedings 
Roles: Author, Editor, 956, Opponent, Creator, 958, Thesis advisor, Other
Classifications: QA76.76.C65, 005.453
Publication Timeline
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Most widely held works by Xavier Leroy
Types in compilation : second international workshop, TIC'98, Kyoto, Japan, March 25-27, 1998 : proceedings by Xavier Leroy( Book )

24 editions published between 1998 and 2002 in English and Undetermined and held by 256 WorldCat member libraries worldwide

This book constitutes the thoroughly refereed post-workshop proceedings of the Second International Workshop on Types in Compilation, TIC '98, held in Kyoto, Japan in March 1998. The book presents 13 revised full papers carefully selected during an iterated reviewing process together with three invited papers. The papers are organized in topical sections on typed intermediate languages, program analyses, program transformations and code generation, memory management, partial evaluation and run-time code generation, and distributed computing
Le langage Caml by Pierre Weis( Book )

11 editions published between 1993 and 2005 in French and held by 164 WorldCat member libraries worldwide

The CAML LIGHT system release 0.5, documentation and user's manual by Xavier Leroy( Book )

2 editions published in 1992 in English and held by 9 WorldCat member libraries worldwide

The ZINC experiment : an economical implementation of the ML language by Xavier Leroy( Book )

3 editions published in 1990 in English and held by 5 WorldCat member libraries worldwide

Extraction de code fonctionnel certifié à partir de spécifications inductives. by Pierre-Nicolas Tollitte( )

1 edition published in 2013 in French and held by 1 WorldCat member library worldwide

Les outils d'aide à la preuve basés sur la théorie des types permettent à l'utilisateur d'adopter soit un style fonctionnel, soit un style relationnel (c'est-à-dire en utilisant des types inductifs). Chacun des deux styles a des avantages et des inconvénients. Le style relationnel peut être préféré parce qu'il permet à l'utilisateur de décrire seulement ce qui est vrai, de s'abstraire temporairement de la question de la terminaison, et de s'en tenir à une description utilisant des règles. Cependant, une spécification relationnelle n'est pas exécutable.Nous proposons un cadre général pour transformer une spécification inductive en une spécification fonctionnelle, en extrayant à partir de la première une fonction et en produisant éventuellement la preuve de correction de la fonction extraite par rapport à sa spécification inductive. De plus, à partir de modes définis par l'utilisateur, qui permettent de considérer les arguments de la relation comme des entrées ou des sorties (de fonction), nous pouvons extraire plusieurs comportements calculatoires à partir d'un seul type inductif.Nous fournissons également deux implantations de notre approche, l'une dans l'outil d'aide à la preuve Coq et l'autre dans l'environnement Focalize. Les deux sont actuellement distribuées avec leurs outils respectifs
Verification formelle et optimisation de l'allocation de registres by Benoît Robillard( )

1 edition published in 2010 in French and held by 1 WorldCat member library worldwide

The need for trustful programs led to an increasing use of formal verication techniques the last decade, and especially of program proof. However, the code running on the computer is not the source code, i.e. the one written by the developper, since it has to betranslated by the compiler. As a result, the formal verication of compilers is required to complete the source code verication. One of the hardest phases of compilation is register allocation. Register allocation is the phase within which the compiler decides where the variables of the program are stored in the memory during its execution. The are two kinds of memory locations : a limited number of fast-access zones, called registers, and a very large but slow-access stack. The aim of register allocation is then to make a great use of registers, leading to a faster runnable code.The most used model for register allocation is the interference graph coloring one. In this thesis, our objective is twofold : first, formally verifying some well-known interference graph coloring algorithms for register allocation and, second, designing new graph-coloring register allocation algorithms. More precisely, we provide a fully formally veri ed implementation of the Iterated Register Coalescing, a very classical graph-coloring register allocation heuristics, that has been integrated into the CompCert compiler. We also studied two intermediate representations of programs used in compilers, and in particular the SSA form to design new algorithms, using global properties of the graph rather than local criteria currently used in the litterature
Compilation de termes de preuves un (nouveau) mariage entre coq et OCaml by Benjamin Grégoire( Book )

1 edition published in 2003 in French and held by 1 WorldCat member library worldwide

Vérification formelle de validateurs de traduction by Jean-Baptiste Tristan( Book )

1 edition published in 2009 in English and held by 1 WorldCat member library worldwide

Comme tout logiciel, les compilateurs, et tout particulièrement les compilateurs optimisant, peuvent être défectueux. Il est donc possible qu'ils changent la sémantique du programme compilé, et par conséquent ses propriétés. Dans le cadre de développement de logiciels critiques, où des méthodes formelles sont utilisées pour s'assurer qu'un programme satisfait certaines propriétés, et cela avant qu'il soit compilé, cela pose un problème de fond. Une solution à ce problème est de vérifier le compilateur en s'assurant qu'il préserve la sémantique des programmes compilés. Dans cette thèse, nous proposons une méthode nouvelle pour développer des passes de compilations sûres: la vérification formelle de validateurs de traduction. D'une part, cette méthode utilise la vérification formelle à l'aide d'assistant de preuve afin d'offrir le maximum de garanties de sûreté sur le compilateur. D'autre part, elle repose sur l'utilisation de la validation de traduction, où chaque exécution du compilateur est validée a posteriori, une méthode de vérification plus pragmatique qui a permis de vérifier des optimisations avancées. Nous montrons que cette approche nouvelle du problème de la vérification de compilateur est viable, et même avantageuse dans certains cas, à travers quatre exemples d'optimisations réalistes et agressives: le list scheduling, le trace scheduling, le lazy code motion et enfin le software pipelining
Taking architecture and compiler into account in formal proofs of numerical programs by Thi Minh Tuyen Nguyen( )

1 edition published in 2012 in English and held by 1 WorldCat member library worldwide

Sur des architectures récentes, un programme numérique peut donner des réponses différentes en fonction du hardware et du compilateur. Ces incohérences des résultats viennent du fait que chaque calcul en virgule flottante est effectué avec des précisions différentes. Le but de cette thèse est de prouver formellement des propriétés des programmes opérant sur des nombres flottants en prenant en compte l'architecture et le compilateur. Pour le faire, nous avons proposé deux approches différentes. La première approche est de prouver des propriétés des programmes en virgule flottante qui sont vraies sur plusieurs architectures et compilateurs. Cette approche ne considère que les erreurs d'arrondi qui doivent être validées quels que soient l'environnement matériel et le choix du compilateur. Elle est implantée dans la plate-forme Frama-C pour l'analyse statique de code C. La deuxième approche consiste à prouver des propriétés des programmes en analysant leur code assembleur. Nous nous concentrons sur des problèmes et des pièges qui apparaissent sur des calculs en virgule flottante. L'analyse directe du code assembleur nous permet de considérer des caratéristiques dépendant de l'architecture ou du compilateur telle que l'utilisation des registres en précision étendue. Cette approche est implantée comme une sur-couche de la plate-forme Why pour la vérification déductive
Certification of a Tool Chain for Deductive Program Verification by Paolo Herms( )

1 edition published in 2013 in English and held by 1 WorldCat member library worldwide

This thesis belongs to the domain of software verification. The goalof verifying software is to ensure that an implementation, a program,satisfies the requirements, the specification. This is especiallyimportant for critical computer programs, such as control systems forair planes, trains and power plants. Here a malfunctioning occurringduring operation would have catastrophic consequences. Software requirements can concern safety or functioning. Safetyrequirements, such as not accessing memory locations outside validbounds, are often implicit, in the sense that any implementation isexpected to be safe. On the other hand, functional requirementsspecify what the program is supposed to do. The specification of aprogram is often expressed informally by describing in English or someother natural language the mission of a part of the program code.Usually program verification is then done by manual code review,simulation and extensive testing. But this does not guarantee that allpossible execution cases are captured. Deductive program proving is a complete way to ensure soundness of theprogram. Here a program along with its specificationis a mathematical object and its desired properties are logicaltheorems to be formally proved. This way, if the underlying logicsystem is consistent, we can be absolutely sure that the provenproperty holds for the program in any case.Generation of verification conditions is a technique helpingthe programmer to prove the properties he wants about his programs.Here a VCG tool analyses a program and its formal specification andproduces a mathematical formula, whose validity implies the soundnessof the program with respect to its specification. This is particularlyinteresting when the generated formulas can be proved automatically byexternal SMT solvers.This approach is based on works of Hoare and Dijkstra and iswell-understood and shown correct in theory. Deductive verificationtools have nowadays reached a maturity allowing them to be used inindustrial context where a very high level of assurance isrequired. But implementations of this approach must deal with allkinds of language features and can therefore become quite complex andcontain errors -- in the worst case stating that a program correcteven if it is not. This raises the question of the level ofconfidence granted to these tools themselves. The aim of this thesis is to address this question. We develop, inthe Coq system, a certified verification-condition generator (VCG) forACSL-annotated C programs.Our first contribution is the formalisation of an executableVCG for the Whycert intermediate language,an imperative language with loops, exceptions and recursive functionsand its soundness proof with respect to the blocking big-step operational semantics of the language.A second contribution is the formalisation of the ACSL logicallanguage and the semantics of ACSL annotations of Compcert's Clight.From the compilation of ACSL annotated Clight programs to Whycertprograms and its semantics preservation proof combined with a Whycertaxiomatisation of the Compcert memory model results our maincontribution: an integrated certified tool chainfor verification of C~programs on top of Compcert. By combining oursoundness result with the soundness of the Compcert compiler we obtaina Coq theorem relating the validity of the generated proof obligationswith the safety of the compiled assembly code
Program logics for certified compilers by Andrew W Appel( Book )

1 edition published in 2014 in English and held by 1 WorldCat member library worldwide

Separation logic is the twenty-first-century variant of Hoare logic that permits verification of pointer-manipulating programs. This book covers practical and theoretical aspects of separation logic at a level accessible to beginning graduate students interested in software verification. On the practical side it offers an introduction to verification in Hoare and separation logics, simple case studies for toy languages, and the Verifiable C program logic for the C programming language. On the theoretical side it presents separation algebras
Modules mixins, modules et récursion étendue en appel par valeur by Tom Hirschowitz( Book )

1 edition published in 2003 in English and held by 1 WorldCat member library worldwide

Le langage CAML by Pierre Weis( )

1 edition published in 2009 in French and held by 1 WorldCat member library worldwide

Proceedings of the ACM-SIGPLAN Workshop on ML (ML 2005), Tallinn, Estonia, 29 September 2005 by ACM SIGPLAN Workshop on ML( )

1 edition published in 2006 in English and held by 0 WorldCat member libraries worldwide

 
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Types in compilation : second international workshop, TIC'98, Kyoto, Japan, March 25-27, 1998 : proceedings
Alternative Names
Xavier Leroy Frans informaticus

Xavier Leroy fransk ingeniør og informatikar

Xavier Leroy fransk ingeniør og informatiker

Xavier Leroy fransk ingenjör och datavetare

Xavier Leroy French computer scientistand programmer

Ксавье Лерой

Languages
English (34)

French (15)

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