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Algorithms for Synthesis and Testing of Asynchronous Circuits

Author: Luciano Lavagno; Alberto Sangiovanni-Vincentelli
Publisher: Boston, MA : Springer US, 1993.
Series: Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing, 232.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
The design of asynchronous circuits is increasingly important in solving problems such as complexity management, modularity, power consumption and clock distribution in large digital integrated circuits. Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Luciano Lavagno; Alberto Sangiovanni-Vincentelli
ISBN: 9781461532125 1461532124
OCLC Number: 851775272
Description: 1 online resource (xix, 339 pages).
Contents: 1 Introduction --
1.1 Motivation --
1.2 Organization --
2 Overview of The Design Methodology --
2.1 Signal Transition Graphs --
2.2 Signal Transition Graph Synthesis --
2.3 The VMEbus Master Interface Protocol --
2.4 A Signal Transition Graph Specification for the VMEbus Interface --
2.5 The Circuit Implementation of the VMEbus Master Interface --
3 Previous Work --
3.1 Circuit Model Taxonomy --
3.2 Definitions --
3.3 The Huffman Model for Asynchronous Circuits --
3.4 Micropipelines --
3.5 Speed-independent Circuits --
3.6 Delay-insensitive Circuits --
3.7 Hazard Analysis in Asynchronous Circuits --
3.8 Conclusion --
4 The Signal Transition Graph Model --
4.1 A Low-level Model for Asynchronous Systems --
4.2 Modeling Asynchronous Logic Circuits --
4.3 A High-level Behavioral Model for Asynchronous Systems --
4.4 Classification of Models of Asynchronous Circuits --
4.5 Signal Transition Graphs and Change Diagrams --
4.6 Conclusion --
5 The State Encoding Methodology --
5.1 Overview of the State Encoding Methodology --
5.2 From Signal Transition Graphs to Finite State Machines --
5.3 Constrained Finite State Machine Minimization --
5.4 State Signal Insertion --
5.5 Experimental Results --
6 The Synthesis Methodology --
6.1 Hazard Analysis and Signal Transition Graphs --
6.2 Circuit Implementation of the Next State Function --
6.3 Static Hazard Detection in the Circuit Implementation --
6.4 Hazard Elimination by Delay Padding --
6.5 Dynamic Hazard Analysis --
6.6 Experimental Results --
7 The Design For Testability Methodology --
7.1 Definitions and Notation --
7.2 A Procedure Guaranteed to Generate an HFRPDFT Circuit --
7.3 Heuristic Procedures to Improve HFRPDFT Testability --
7.4 A Procedure Guaranteed to Generate an RGDFT Circuit --
7.5 Design for Delay Testability Methodology --
7.6 Experimental Results --
8 Conclusions --
References.
Series Title: Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing, 232.
Responsibility: by Luciano Lavagno, Alberto Sangiovanni-Vincentelli.

Abstract:

The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex- ploring the possibility of designing asynchronous circuits.  Read more...

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