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Applications of VHDL to Circuit Design

Author: Randolph E Harr; Alec G Stanculescu
Publisher: Boston, MA : Springer US, 1991.
Edition/Format:   eBook : Document : EnglishView all editions and formats
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Randolph E Harr; Alec G Stanculescu
ISBN: 9781461539643 1461539641
OCLC Number: 851823556
Description: 1 online resource (xxi, 232 pages)
Contents: 1. Switch-Level Modeling in VHDL --
1.1 Introduction --
1.2 Advanced Simulator Programming --
1.3 Switch-Level Package --
1.4 Distributed Algorithm for Pass-transistor --
1.5 VHDL Implementation of Distributed Algorithm --
1.6 Examples of Switch-level Networks --
1.7 Future Research --
1.8 Conclusion --
1.9 References --
2. Modeling of Transmission Line Effects in Digital Circuits --
2.1 Introduction --
2.2 Underlying Concepts and Structure --
2.3 Behavioral Models --
2.4 Application of Transmission Line Behaviors --
2.5 Summary --
References --
3. Behavior Modeling of Mixed Analog-Digital Circuits --
3.1 Introduction --
3.2 Simulation Model --
3.3 Design Verification Methodology --
3.4 Application of Analog-Digital Behaviors --
3.5 Summary --
References --
4. Modeling of Analog-Digital Loops in VHDL --
4.1 introduction --
4.2 AGC Loop Behavioral Models --
4.3 Application of Automatic Gain Control Loops --
4.4 Phase-Locked Loop Behavioral Models --
4.5 Application of Phase-Locked Loop --
4.6 Summary --
References --
5. Modeling Style Issues for Synthesis --
5.1 What is HDL Synthesis? --
5.2 Applying HDL Synthesis Technology --
5.3 An HDL Synthesis Policy --
5.4 Synthesis of Register Transfer Level Constructs --
5.5 Synthesis Style Issues in VHDL --
5.6 A Complete Example --
5.7 Closing Remarks --
6. Modeling of Standard Component Libraries --
6.1 Structure of Model Libraries --
6.2 Relevant Issues in Logic Simulation --
6.3 Layers of Abstraction --
6.4 Independence from Physical Packaging --
6.5 Strength/Level Values Set Independence --
6.6 Independence from Timing Parameter Values --
6.7 Toward a Standard --
6.8 Summary --
7. Anomalies in VHDL and How to Address Them --
7.1 Common Misconceptions about VHDL --
7.2 VHDL Language Inconsistencies --
7.3 Summary --
7.4 References.
Responsibility: edited by Randolph E. Harr, Alec G. Stanculescu.

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