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Architecture-independent loop parallelisation

Author: Radu C Calinescu
Publisher: London ; New York : Springer, ©2000.
Series: CPHC/BCS distinguished dissertations.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

This title looks at architecture-independent programming and automatic parallelization. Building on advances in both areas, the title proposes a unified approach to parallelization of scientific  Read more...

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Additional Physical Format: Online version:
Calinescu, Radu C., 1968-
Architecture-independent loop parallelisation.
London ; New York: Springer, ©2000
(OCoLC)651871384
Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Radu C Calinescu
ISBN: 1852332840 9781852332846
OCLC Number: 44883521
Description: xviii, 172 pages : illustrations ; 24 cm.
Contents: 1. Introduction --
2. The Bulk-Synchronous Parallel Model --
3. Data Dependence Analysis and Code Transformation --
4. Communication Overheads in Loop Nest Scheduling --
5. Template-Matching Parallelisation --
6. Generic Loop Nest Parallelisation --
7. A Strategy and a Tool for Architecture-Independent Loop Parallelisation --
8. The Effectiveness of Architecture-Independent Loop Parallelisation --
9. Conclusions --
App. A. Theorem proofs --
App. B. Syntax of the BSPscheduler input language --
App. C. Syntax of the BSPscheduler output language --
App. D. Automatically generated code for Example 7.5.
Series Title: CPHC/BCS distinguished dissertations.
Responsibility: Radu C. Calinescu.

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