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The cache coherence problem in shared-memory multiprocessors : hardware solutions

Author: Milo Tomašević; Veljko Milutinović
Publisher: Los Alamitos, Calif. : IEEE Computer Society Press, ©1993.
Edition/Format:   Print book : EnglishView all editions and formats
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Additional Physical Format: Online version:
Cache-coherence problem in shared-memory multiprocessors.
Los Alamitos, Calif. : IEEE Computer Society Press, ©1993
(OCoLC)654318120
Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Milo Tomašević; Veljko Milutinović
ISBN: 0818640928 9780818640926 081864091X 9780818640919
OCLC Number: 27431472
Notes: "IEEE Computer Society Press order number 4092-01"--Title page verso.
Description: xii, 431 pages : illustrations ; 29 cm
Contents: Ch. 1. Introductory Issues --
Design of CPU Cache Memories / A.J. Smith --
Synchronization, Coherence, and Event Ordering in Multiprocessors / M. Dubois, C. Scheurich and F.A. Briggs --
Effects of Cache Coherency in Multiprocessors / M. Dubios and F.A. Briggs --
A Survey of Cache Coherence Schemes for Multiprocessors / P. Stenstrom --
Hardware Solutions for Cache Coherence in Shared-Memory Multiprocessor Systems / M. Tomasevic and V. Milutinovic --
Ch. 2. Memory Reference Characteristics of Parallel Programs --
A Characterization of Sharing in Parallel Programs and its Application to Coherency Protocol Evaluation / S.J. Eggers and R.H. Katz --
Memory-Reference Characteristics of Multiprocessor Applications under MACH / A. Agarwal and A. Gupta --
The Effect of Sharing on the Cache and Bus Performance of Parallel Programs / S.J. Eggers and R.H. Katz --
Ch. 3. Directory Cache Coherence Protocols --
Cache System Design in the Tightly Coupled Multiprocessor System / C.K. Tang --
A New Solution to Coherence Problems in Multicache Systems / L.M. Censier and P. Feautrier --
An Economical Solution to the Cache Coherence Problem / J. Archibald and J.-L. Baer --
An Empirical Evaluation of Two Memory-Efficient Directory Methods / B.W. O'Krafka and A.R. Newton --
Two Economical Directory Schemes for Large-Scale Cache-Coherent Multiprocessors / Y.-C. Maa, D.K. Pradhan and D. Thiebaut --
Directory-Based Cache Coherence in Large-Scale Multiprocessors / D. Chaiken, C. Fields, K. Kurihara and A. Agarwal --
Ch. 4. Snoopy Cache Coherence Protocols --
Using Cache Memory to Reduce Processor-Memory Traffic / J.R. Ooodman --
A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories / M.S. Papamarcos and J.H. Patel --
Dynamic Decentralized Cache Schemes for MIMD Parallel Processors / L. Rudolph and Z. Segall --
Implementing a Cache Consistency Protocol / R.H. Katz, S.J. Eggers, D.A. Wood, C.L. Perkins and R.G. Sheldon --
Firefly: A Multiprocessor Workstation / C.P. Thacker, L.C. Stewart and E.H. Satterthwaite --
Multiprocessor Cache Synchronization: Issues, Innovations, Evolution / P. Bitar and A. Despain --
Coherency For Multiprocessor Virtual Address Caches / J.R. Goodman --
A Class of Compatible Cache Consistency Protocols and Their Support by the IEEE Futurebus / P. Sweazey and A.J. Smith --
Competitive Snoopy Caching / A.R. Karlin, M.S. Manasse, L. Rudolph and D.D. Sleator --
Ch. 5. Coherence in Multilevel Cache Hierarchies --
On the Inclusion Properties for Multi-Level Cache Hierarchies / J.-L. Baer and W.-H. Wang --
Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy / W.-H. Wang, J.-L. Baer and H.M. Levy --
Ch. 6. Cache Coherence Schemes in Large-Scale Multiprocessors --
Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors / A.W. Wilson, Jr. --
A Cache Coherence Approach For Large Multiprocessor Systems / J.K. Archibald --
The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor / J.R. Goodman and P.J. Woest --
The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor / D. Lenoski, J. Laudon, K. Gharachorloo, A. Gupta and J. Hennessy --
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes / A. Gupta, W.-D. Weber and T. Mowry --
LimitLESS Directories: A Scalable Cache Coherence Scheme / D. Chaiken, J. Kubiatowitz and A. Agarwal --
Ch. 7. Evaluation of Hardware Cache Coherence Schemes --
Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model / J. Archibald and J.-L. Baer --
A Simulation Study of Snoopy Cache Coherence Protocols / M. Tomasevic and V. Milutinovic --
Evaluating the Performance of Four Snooping Cache Coherency Protocols / S.J. Eggers and R.H. Katz --
An Evaluation of Directory Schemes for Cache Coherence / A. Agarwal, R. Simoni, J. Rennessy and M. Horowitz --
Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures / P. Stenstrom, T. Joe and A. Gupta --
An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols / M.K. Vernon, E.D. Lazowska and J. Zahorjan --
Comparison of Hardware and Software Cache Coherence Schemes / S.V. Adve, V.S. Adve, M.D. Hill and M.K. Vernon.
Responsibility: [edited by] Milo Tomašević and Veljko Milutinović.

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