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CAD geometry data exchange using STEP : realisation of interface processors

Author: H J Helpenstein
Publisher: Berlin ; New York : Springer-Verlag, ©1993.
Series: Research reports ESPRIT., Project 2195,, Subseries PDT., CADEX ;, vol. 1.
Edition/Format:   Print book : EnglishView all editions and formats
Database:WorldCat
Summary:

A report of progress achieved by a European consortium of CAD vendors and users who have attempted to create a new worldwide standard for data exchange in computer integrated manufacturing. The  Read more...

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Additional Physical Format: Online version:
CAD geometry data exchange using STEP.
Berlin ; New York : Springer-Verlag, ©1993
(OCoLC)624396888
Document Type: Book
All Authors / Contributors: H J Helpenstein
ISBN: 3540569022 9783540569022 0387569022 9780387569024
OCLC Number: 30397210
Description: xiv, 432 pages : illustrations ; 24 cm.
Contents: 1. Introduction.- 2. Application Protocols and STEP relations.- 2.1 Entity tables and mapping to STEP.- 2.1.1 Objectives for the table of entities.- 2.1.2 The table of native entities mapped to STEP.- 2.1.3 Other CAD model entities which require a STEP model transfer.- 2.1.4 A general association capability.- 2.1.5 Considerations on the attribute association of STEP entities.- 2.2 Work in the ISO and the concept of Application Protocols.- 2.2.1 Overview on CADEX contributions and activities to ISO/STEP.- 2.2.2 The Concept of an Application Protocol.- 2.2.3 Table of contents of an ISO Application Protocol.- 2.2.4 The Mechanical Design Application Protocol concept.- 2.2.5 List of open STEP issues from CADEX point of view.- 2.2.6 Recommendations to STEP.- 2.2.7 Other ISO work.- 2.3 ISO Application Protocols.- 2.3.1 Application Protocol for mechanical design using boundary representation.- 2.3.2 Application Protocol for mechanical design using surface representation.- 2.3.3 Application Protocol for mechanical design using wirefame representation.- 2.3.4 EXPRESS long form of the Product Structure module.- 2.4 Other CADEX Application Protocols.- 2.5 Relationships between Application Protocols.- 2.5.1 Domains of the Application Protocols.- 2.5.2 Conversion between different Application Protocols.- 2.5.3 Shape entites from multiple APs in single files.- 2.5.4 Application Interpreted Constructs.- 3. Common Tool Kit.- 3.1 Introduction.- 3.2 The architecture of the CADEX pre- and postprocessors.- 3.2.1 Overview.- 3.2.2 Description of the architecture.- 3.2.3 Organisation of the development.- 3.3 Technical description.- 3.3.1 IDS.- 3.3.2 Scanner and parser.- 3.3.3 Formatter.- 3.3.4 Checker.- 3.3.5 Statistics tools.- 3.3.6 Conversion tools.- 3.3.6.1 General remarks on conversion tools.- 3.3.6.2 Conversion tools by SI.- 3.3.6.3 Conversion tools by GfS.- 3.3.6.4 Conversion tools by FEGS Ltd.- 3.4 User's Guide.- 3.4.1 IDS.- 3.4.2 Scanner and parser.- 3.4.3 Formatter.- 3.4.4 Checker.- 3.4.5 Statistics tools.- 3.4.6 User's guide of SI tools.- 3.4.7 User's guide of GfS tools.- 3.4.8 User's guide of FEGS tools.- 4. Development of Processors.- 4.1 Det Norske Veritas Research.- 4.1.1 Introduction.- 4.1.2 Processor architecture.- 4.1.3 Post-processor backend.- 4.1.4 Post-processor conversion.- 4.1.5 Pre-processor frontend.- 4.1.6 Available processors.- 4.1.7 Future.- 4.1.8 Examples.- 4.2 DISEL.- 4.2.1 Introduction.- 4.2.2 Development environment.- 4.2.3 Processors description.- 4.3 FEGS Ltd.- 4.3.1 Introduction.- 4.3.2 The status of FAM.- 4.3.3 The processors that have been developed.- 4.3.4 Requirements to the processors.- 4.3.5 System architecture.- 4.3.6 User interface and software operation.- 4.3.7 Transfer between IDS and FAM.- 4.3.8 Conversions between IDS and FAM.- 4.3.9 Conversions between STEP entities on IDS.- 4.3.10 The support of the boundary-representation AP, ISO 10303-204.- 4.3.11 The support of the surface AP, ISO 10303-205.- 4.3.12 The support of the wire frame AP, ISO 10303-206.- 4.3.13 The support of the compound b-rep AP.- 4.3.14 Current status.- 4.3.15 The experience gained in the project.- 4.3.16 Future plans, FAM and FAMexchange..- 4.4 Gesellschaft fur Strukturanalyse.- 4.4.1 Introduction.- 4.4.2 Models to be covered.- 4.4.3 Functionality.- 4.4.4 Implementation and Test.- 4.5 Hewlett-Packard.- 4.5.1 Introduction.- 4.5.2 HP's ME30 STEP pre-processor.- 4.5.3 HP's SolidDesigner STEP post-processor..- 4.5.4 HP's SolidDesigner STEP pre-processor.- 4.5.5 Examples of model exchange.- 4.5.6 References.- 4.6 ISYKON and PROCAD.- 4.6.1 Introduction.- 4.6.2 The pre-processors.- 4.6.3 The post-processors.- 4.6.4 The dialogue language.- 4.6.5 Integrated test tools.- 4.6.6 Summary.- 4.7 ITALCAD.- 4.7.1 Introduction.- 4.7.2 Processor architecture.- 4.7.3 Processors built.- 4.7.4 Implementation and test.- 4.8 Kongsberg 3D Partner A.S.- 4.8.1 Introduction.- 4.8.2 System architecture.- 4.8.3 Pre-processor implementation.- 4.8.4 Post-processor implementation.- 4.8.5 Error and log handling.- 4.8.6 Testing.- 4.8.8 Comments and exploitation of results.- 4.9 Senter for Industriforskning.- 4.9.1 Summary and applicable documents.- 4.9.2 The SISL system.- 4.9.3 Requirements for the SISL-STEP interface.- 4.9.4 Architecture of the SISL-STEP processors.- 4.9.5 General information on the SISL-STEP processors.- 4.9.6 Processor details.- 4.10 Siemens-Nixdorf-Informationssysteme.- 4.10.1 Overview.- 4.10.2 System and processor architecture.- 4.10.3 Processor for SF-AP.- 4.10.4 Processor for BRep-AP.- 5. Test and Validation.- 5.1 Introduction.- 5.2 User acceptance testing.- 5.2.1 The user roles in CADEX.- 5.2.2 Types of tests.- 5.2.3 Test data.- 5.2.4 Test procedures.- 5.2.5 Software tool support.- 5.3 Conformance testing.- 5.3.1 Introduction and definition.- 5.3.2 Motivation for performing conformance testing.- 5.3.3 Influence of the CEC funded CTS2 project.- 5.3.4 Types of tests.- 5.3.5 AP conformance requirements.- 5.3.6 AP test purposes.- 5.3.7 Test data and procedures.- 5.4 The FIAT test library.- 5.4.1 Choice of the models.- 5.4.2 Model generation description (MGD).- 5.4.3 Data transfer evaluation criteria.- 5.5 Test plan and results.- 5.5.1 Test plan.- 5.5.2 Test results of Gesellschaft fu1. Introduction.- 2. Application Protocols and STEP relations.- 2.1 Entity tables and mapping to STEP.- 2.1.1 Objectives for the table of entities.- 2.1.2 The table of native entities mapped to STEP.- 2.1.3 Other CAD model entities which require a STEP model transfer.- 2.1.4 A general association capability.- 2.1.5 Considerations on the attribute association of STEP entities.- 2.2 Work in the ISO and the concept of Application Protocols.- 2.2.1 Overview on CADEX contributions and activities to ISO/STEP.- 2.2.2 The Concept of an Application Protocol.- 2.2.3 Table of contents of an ISO Application Protocol.- 2.2.4 The Mechanical Design Application Protocol concept.- 2.2.5 List of open STEP issues from CADEX point of view.- 2.2.6 Recommendations to STEP.- 2.2.7 Other ISO work.- 2.3 ISO Application Protocols.- 2.3.1 Application Protocol for mechanical design using boundary representation.- 2.3.2 Application Protocol for mechanical design using surface representation.- 2.3.3 Application Protocol for mechanical design using wirefame representation.- 2.3.4 EXPRESS long form of the Product Structure module.- 2.4 Other CADEX Application Protocols.- 2.5 Relationships between Application Protocols.- 2.5.1 Domains of the Application Protocols.- 2.5.2 Conversion between different Application Protocols.- 2.5.3 Shape entites from multiple APs in single files.- 2.5.4 Application Interpreted Constructs.- 3. Common Tool Kit.- 3.1 Introduction.- 3.2 The architecture of the CADEX pre- and postprocessors.- 3.2.1 Overview.- 3.2.2 Description of the architecture.- 3.2.3 Organisation of the development.- 3.3 Technical description.- 3.3.1 IDS.- 3.3.2 Scanner and parser.- 3.3.3 Formatter.- 3.3.4 Checker.- 3.3.5 Statistics tools.- 3.3.6 Conversion tools.- 3.3.6.1 General remarks on conversion tools.- 3.3.6.2 Conversion tools by SI.- 3.3.6.3 Conversion tools by GfS.- 3.3.6.4 Conversion tools by FEGS Ltd.- 3.4 User's Guide.- 3.4.1 IDS.- 3.4.2 Scanner and parser.- 3.4.3 Formatter.- 3.4.4 Checker.- 3.4.5 Statistics tools.- 3.4.6 User's guide of SI tools.- 3.4.7 User's guide of GfS tools.- 3.4.8 User's guide of FEGS tools.- 4. Development of Processors.- 4.1 Det Norske Veritas Research.- 4.1.1 Introduction.- 4.1.2 Processor architecture.- 4.1.3 Post-processor backend.- 4.1.4 Post-processor conversion.- 4.1.5 Pre-processor frontend.- 4.1.6 Available processors.- 4.1.7 Future.- 4.1.8 Examples.- 4.2 DISEL.- 4.2.1 Introduction.- 4.2.2 Development environment.- 4.2.3 Processors description.- 4.3 FEGS Ltd.- 4.3.1 Introduction.- 4.3.2 The status of FAM.- 4.3.3 The processors that have been developed.- 4.3.4 Requirements to the processors.- 4.3.5 System architecture.- 4.3.6 User interface and software operation.- 4.3.7 Transfer between IDS and FAM.- 4.3.8 Conversions between IDS and FAM.- 4.3.9 Conversions between STEP entities on IDS.- 4.3.10 The support of the boundary-representation AP, ISO 10303-204.- 4.3.11 The support of the surface AP, ISO 10303-205.- 4.3.12 The support of the wire frame AP, ISO 10303-206.- 4.3.13 The support of the compound b-rep AP.- 4.3.14 Current status.- 4.3.15 The experience gained in the project.- 4.3.16 Future plans, FAM and FAMexchange..- 4.4 Gesellschaft fur Strukturanalyse.- 4.4.1 Introduction.- 4.4.2 Models to be covered.- 4.4.3 Functionality.- 4.4.4 Implementation and Test.- 4.5 Hewlett-Packard.- 4.5.1 Introduction.- 4.5.2 HP's ME30 STEP pre-processor.- 4.5.3 HP's SolidDesigner STEP post-processor..- 4.5.4 HP's SolidDesigner STEP pre-processor.- 4.5.5 Examples of model exchange.- 4.5.6 References.- 4.6 ISYKON and PROCAD.- 4.6.1 Introduction.- 4.6.2 The pre-processors.- 4.6.3 The post-processors.- 4.6.4 The dialogue language.- 4.6.5 Integrated test tools.- 4.6.6 Summary.- 4.7 ITALCAD.- 4.7.1 Introduction.- 4.7.2 Processor architecture.- 4.7.3 Processors built.- 4.7.4 Implementation and test.- 4.8 Kongsberg 3D Partner A.S.- 4.8.1 Introduction.- 4.8.2 System architecture.- 4.8.3 Pre-processor implementation.- 4.8.4 Post-processor implementation.- 4.8.5 Error and log handling.- 4.8.6 Testing.- 4.8.8 Comments and exploitation of results.- 4.9 Senter for Industriforskning.- 4.9.1 Summary and applicable documents.- 4.9.2 The SISL system.- 4.9.3 Requirements for the SISL-STEP interface.- 4.9.4 Architecture of the SISL-STEP processors.- 4.9.5 General information on the SISL-STEP processors.- 4.9.6 Processor details.- 4.10 Siemens-Nixdorf-Informationssysteme.- 4.10.1 Overview.- 4.10.2 System and processor architecture.- 4.10.3 Processor for SF-AP.- 4.10.4 Processor for BRep-AP.- 5. Test and Validation.- 5.1 Introduction.- 5.2 User acceptance testing.- 5.2.1 The user roles in CADEX.- 5.2.2 Types of tests.- 5.2.3 Test data.- 5.2.4 Test procedures.- 5.2.5 Software tool support.- 5.3 Conformance testing.- 5.3.1 Introduction and definition.- 5.3.2 Motivation for performing conformance testing.- 5.3.3 Influence of the CEC funded CTS2 project.- 5.3.4 Types of tests.- 5.3.5 AP conformance requirements.- 5.3.6 AP test purposes.- 5.3.7 Test data and procedures.- 5.4 The FIAT test library.- 5.4.1 Choice of the models.- 5.4.2 Model generation description (MGD).- 5.4.3 Data transfer evaluation criteria.- 5.5 Test plan and results.- 5.5.1 Test plan.- 5.5.2 Test results of Gesellschaft fur Strukturanalyse..- 5.5.3 Test results of Siemens Nixdorf..- 5.5.4 Test results of Senter for Industriforskning.- 5.5.5 Test results of Kongsberg 3D Partner A.S.- 5.5.6 Test results of Italcad.- 5.5.7 Test results of Procad and Isykon.- 5.5.8 Test results of Hewlett Packard.- 5.5.9 Test results of DISEL.- 5.6 Bibliography.
Series Title: Research reports ESPRIT., Project 2195,, Subseries PDT., CADEX ;, vol. 1.
Responsibility: H.J. Helpenstein, ed.
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