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Circuit and interconnect design for RF and high bit-rate applications

Author: Hugo Veenstra; John R Long
Publisher: [Dordrecht] : Springer, ©2008.
Series: Analog circuits and signal processing series.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the `interconnect') and circuit design. Many  Read more...

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Document Type: Book
All Authors / Contributors: Hugo Veenstra; John R Long
ISBN: 9781402068829 1402068824 1402068840 9781402068843 9048177502 9789048177509
OCLC Number: 191753878
Description: xii, 246 pages : illustrations ; 25 cm.
Contents: Preface. 1. The Challenge. 1.1 Interconnect. 1.2 Device Metrics. 1.3 Cross-Connect Switches. 1.4 Transistor Operation above BVCEO. 1.5 CML circuits, PRBS generator. 1.6 Oscillators. 1.7 Outline of the book. References. 2. Interconnect Modelling, Analysis and Design. 2.1 Introduction. 2.2 Transmission Line Theory. 2.3 When to Include Transmission Line Effects. 2.4 Secondary Effects. 2.5 Resistivity-Frequency Mode Chart for a Microstrip Line. 2.6 Preferred Transmission Line Configurations. 2.7 Applying the Skin Effect Formulas to a SiGeBiCMOS Process. 2.8 Models including Skin Effect. 2.9 Signal Transfer Across a Transmission Line. 2.10 Interconnect Test Structures. 2.11 Modelling and Considerations of Digital Interconnect. 2.12 Circuit and Interconnect Design Flow. 2.13 Conclusions and Outlook. References. 3. Device Metrics. 3.1 Introduction. 3.2 Miller Effects. 3.3 Definitions based on y-Parameters. 3.4 Approximate Formulas for the Device Metrics. 3.5 Optimising a Technology for FA. 3.6 Relationship Between FA, FT and FMAX. 3.7 Trends in Device Metrics. 3.8 Other Trends. 3.9 Bipolar versus RF-CMOS. 3.10 Conclusions and Outlook. References. 4. Cross-Connect Switch Design. 4.1 Introduction. 4.2 Switch Matrix Design. 4.3 Buffer Circuits. 4.4 Complete RF Signal Path. 4.5 Supply Decoupling. 4.6 Experimental Results. 4.7 Conclusions and Outlook. 5. Bias Circuits Tolerating Output Voltages above BVCEO. 5.1 Introduction. 5.2 Principle of Collector-Base Avalanche Current. 5.3 Analysis of Simple 2-Transistor Current Mirrors. 5.4 Analysis of Current Mirrors with Internal Buffer. 5.5 Avalanche Current Compensation. 5.6 Conclusions and Outlook. 6. Design of Synchronous High Speed CML Circuits. 6.1 Introduction. 6.2 PRBS Background. 6.3 InP Technology. 6.4 PRBS Generator Design. 6.5 Experimental Results. 6.6 Distributed Capacitive Loading Reviewed. 6.7 Conclusionsand Outlook. References. 7. Analysis and Design of High Frequency LC-VCOs. 7.1 Introduction. 7.2 Input Impedance of a Cross-Coupled Differential Pair. 7.3 Input Impedance of a Capacitively-Loaded Emitter Follower. 7.4 Combining Negative Resistance and Output Buffer Functions. 7.5 LC-VCO Operating at a Frequency Close to FCROSS. 7.6 LC-VCO Operating at a Frequency Above FCROSS. 7.7 I/Q Signal Generation. 7.8 Conclusions and Outlook. References. Glossary. Appendix A. Index.
Series Title: Analog circuits and signal processing series.
Responsibility: Hugo Veenstra, John R. Long.

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