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CMOS and beyond : logic switches for terascale integrated circuits

Author: Tsu-Jae King Liu; Kelin Kuhn
Publisher: Cambridge, Untied Kingdom : Cambridge University Press, [2015]
Edition/Format:   Print book : EnglishView all editions and formats
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Learn how to overcome existing logic switch design challenges with this in-depth, accessible, tutorial-style overview of the most promising successors to modern CMOS technology, written by leading  Read more...

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Document Type: Book
All Authors / Contributors: Tsu-Jae King Liu; Kelin Kuhn
ISBN: 9781107043183 1107043182
OCLC Number: 881387445
Description: xvii, 420 pages : illustrations ; 26 cm
Contents: Section I CMOS circuits and technology limits --
1. Energy efficiency limits of digital circuits based on CMOS transistors / Elad Alon --
1.1. Overview --
1.2. Energy-performance trade-offs in digital circuits --
1.3. Design techniques for energy efficiency --
1.4. Energy limits and conclusions --
References --
2. Beyond transistor scaling: alternative device structures for the terascale regime / Kelin J. Kuhn --
2.1. Introduction --
2.2. Alternative device structures --
2.2.1. HEMT --
2.2.2. Gallium nitride --
2.2.3. Ferroelectric-dielectric gate stacks --
2.2.4. Electrochemical devices --
2.2.5. Impact ionization devices --
2.2.6. Tunnel FET --
2.2.7. Metal source/drain devices --
2.2.8. Relays --
2.3. Summary --
References --
3. Benchmarking alternative device structures for the terascale regime / Kelin J. Kuhn --
3.1. Introduction --
3.2. Scaling potential of alternative device structures --
3.2.1. High electron mobility transistors (HEMT) --
3.2.2. Gallium nitride (GaN) transistors --
3.2.3. Negative capacitance (Fe-gate) transistors --
3.2.4. Electrochemical transistors --
3.2.5. Impact ionization metal-oxide semi-conductor (IMOS) transistors --
3.2.6. Tunnel field effect transistors (TFETs) --
3.2.7. Metal source/drain transistors --
3.2.8. Relays --
3.3. Scaling potential of comparison devices --
3.3.1. Ultra-thin body (UTB) transistors --
3.3.2. Gate-all-around (GAA) transistors --
3.3.3. Junctionless accumulation mode (JAM) transistors --
3.3.4. Thin-film transistors --
3.4. Evaluation metrics --
3.5. Benchmarking results --
3.6. Conclusions --
References --
4. Extending CMOS with negative capacitance / Sayeef Salahuddin --
4.1. Introduction --
4.2. Intuitive picture --
4.2.1. Why negative capacitance? --
4.2.2. Reduction of sub-threshold swing --
4.2.3. How can a ferroelectric material give negative capacitance? --
4.2.4. How can we stabilize a ferroelectric material in a state of negative capacitance? --
4.3. Theoretical framework --
4.3.1. Temperature dependence --
4.4. Experimental work --
4.5. Negative capacitance transistors --
4.6. Concluding remarks --
Acknowledgments --
References --
Section II Tunnelling devices --
5. Designing a low-voltage, high-current tunnelling transistor / Eli Yablonovitch --
5.1. Introduction --
5.2. Tunnelling barrier thickness modulation steepness --
5.3. Energy filtering switching mechanism --
5.3.1. Minimum effective bandgap --
5.4. Measuring the electronic transport band edge steepness --
5.5. Collecting spatial inhomogeneity --
5.6. p-n junction dimensionality --
5.6.1. 1D-1Dend junction --
5.6.2. Energy-dependent tunnelling probability --
5.6.3. 3D-3D bulk junction --
5.6.4. 2D-2Dedge junction --
5.6.5. 0D-1D junction --
5.6.6. 2D-3D junction --
5.6.7. 1D-2D junction --
5.6.8. 0D-0D junction --
5.6.9. 2D-2Dface junction --
5.6.10. 1D-1Dedge junction --
5.6.11. Trade-off between current, device size, and level broadening --
5.6.12. Comparing the different dimensionalities --
5.7. Building a full tunnelling field effect transistor --
5.7.1. Minimum voltage required --
5.7.2. Sub-threshold swing voltage --
5.7.3. On-state conductance --
5.8. Maximizing the gate efficiency --
5.8.1. Lateral TFET gate efficiency --
5.8.2. Vertical TFET gate efficiency --
5.8.3. Bilayer TFET gate efficiency --
5.9. Other design issues to avoid --
5.10. Conclusions --
Acknowledgment --
References --
6. Tunnel transistors / Gerhard Klimeck --
6.1. Introduction --
6.1.1. Need for low-voltage and sub-threshold swing --
6.1.2. Scope --
6.2. Tunnel FET --
6.2.1. Physical principles --
6.2.2. Kane-Sze on-current --
6.3. Materials and doping trade-offs --
6.3.1. Homojunction on-current vs. material --
6.3.2. Optimum TFET bandgap --
6.3.3. Doping --
6.3.4. Heterojunctions --
broken-gap benefit --
6.4. Geometrical considerations and gate electrostatics --
6.4.1. Tunnel junction perpendicular to the gate --
6.4.2. Tunnel junction parallel to the gate --
6.4.3. p-TFET --
6.5. Non-idealities --
6.5.1. Traps --
6.5.2. Band tails/phonons --
6.5.3. Interface roughness --
6.5.4. Alloy disorder --
6.5.5. Variability --
6.6. Experimental results --
6.7. Conclusions --
Acknowledgments --
References --
7. Graphene and 2D crystal tunnel transistors / Debdeep Jena --
7.1. What is a low-power switch? --
7.2. Brief review of 2D crystal materials and devices --
7.3. Carbon nanotubes and graphene nanoribbons --
7.3.1. First demonstration of less than 60mV/dec sub-threshold swing in TFETs with carbon nanotubes --
7.3.2. Zener tunnelling in carbon nanotubes and graphene nanoribbons --
7.3.3. TFET device structure and semi-classical modelling --
7.3.4. Geometry and doping dependence, optimization, and benchmarks --
7.3.5. Non-ideal effects --
7.4. Atomically-thin body transistors --
7.4.1. In-plane tunnelling transport in 2D crystals --
7.4.2. In-plane 2D crystal TFETs --
7.5. Interlayer tunnelling transistors --
7.5.1. Interlayer tunnelling between graphene layers --
7.5.2. Symmetric tunnelling field effect transistor (SymFET) --
7.5.3. Bilayer pseudospin FETs (BiSFETs) --
7.5.4. Experimental progress of interlayer tunnelling transistors --
7.5.5. Challenges --
7.6. Internal charge and voltage gain steep devices --
7.7. Conclusions --
References --
8. Bilayer pseudospin field effect transistor / Sanjay K. Bannerjee --
8.1. Introduction --
8.2. Overview --
8.2.1. Condensate formation and low-voltage NDR --
8.2.2. Device layout and compact modelling --
8.2.3. BiSFET compatible circuits and circuit simulation results --
8.2.4. BiSFET technology --
8.3. Essential physics --
8.3.1. Condensate formation in bilayer graphene --
8.3.2. Low-voltage NDR --
8.4. BiSFET design and compact modelling --
8.4.1. BiSFET (and BiS junction) design --
8.4.2. Compact circuit models --
8.5. BiSFET logic circuits and simulation results --
8.5.1. BiSFETs logic circuit basics: how to use and how not to use BiSFETs --
8.5.2. Circuit simulation results --
8.6. Technology --
8.7. Conclusions --
Acknowledgments --
References --
Section III Alternative field effect devices --
9. Computation and learning with metal-insulator transitions and emergent phases in correlated oxides / Shriram Ramanathan --
9.1. Overview --
9.1.1. Introduction --
9.1.2. Outline of chapter --
9.2. Metal-insulator transition in vanadium dioxide --
9.2.1. Electronic and structural transition --
9.2.2. Proposed mechanisms of the phase transition --
9.3. Field effect devices using phase transitions --
9.3.1. Mott FET: theory and challenges --
9.3.2. Solid-state VO2-based FETs --
9.3.3. Ionic liquid-gated VO2 FETs --
9.4. Two-terminal devices utilizing phase transitions --
9.4.1. Threshold switches, resistive memory, and neural computing --
9.5. Neural circuits --
9.6. Conclusions --
References --
10. The piezoelectronic transistor / Dennis M. Newns --
10.1. Introduction --
10.2. How it works --
10.3. Physics of PET materials --
10.3.1. Polarization rotation in relaxor-based piezoelectric single crystals --
10.3.2. 4f 5d electronic promotion under pressure in rare earth chalcogenide piezoresistors --
10.3.3. Equivalent sub-threshold slope --
10.4. PET dynamics --
10.4.1. Electromechanical (Tiersten) equations --
10.4.2. Simulation of logic circuits --
10.4.3. Electromechanical lumped-element circuit model for PET --
10.4.4. Mechanical and electrical parasitics --
10.5. Materials and device fabrication --
10.5.1. SmSe --
10.5.2. PMT-PT --
10.5.3. PET fabrication --
progress and issues --
10.6. Performance estimation --
10.7. Discussion --
Acknowledgments --
References --
11. Mechanical switches / Tsu-Jae King Liu --
11.1. Introduction --
11.2. Relay structure and operation --
11.2.1. Electrostatically-actuated relays --
11.2.2. Relay designs --
11.3. Relay process technology --
11.3.1. Materials selection and process integration challenges --
11.3.2. Relay process flow --
11.4. Relay design optimization for digital logic --
11.4.1. Design for improved electrostatics --
11.4.2. Design for highly-compact circuits --
11.4.3. Design for low-voltage operation --
11.5. Relay combinational logic circuits --
11.5.1. Complementary relay inverter circuit --
11.5.2. CMOS-like circuit design --
11.5.3. Multi-input/multi-output design --
11.6. Relay scaling perspective --
References --
Section IV Spin-based devices --
12. Nanomagnetic logic: from magnetic ordering to magnetic computing / Wolfgang Porod --
12.1. Introduction and motivation --
12.1.1. Magnetic computing defined --
12.1.2. Qualitative description --
12.1.3. Why NML? Benefits and challenges --
12.1.4. Outline of the chapter --
12.2. Single-domain nanomagnets as binary switching elements --
12.3. Behaviour of coupled nanomagnets --
12.4. Engineering the coupling: gates and concatenated gates --
12.5. Errors in magnetic ordering --
12.6. Controlling magnetic ordering: clocking of nanomagnets --
12.6.1. Control of speed and error rates using hard-axis clocking --
12.6.2. Energetics of NML clocking --
12.7. Computing systems from NML --
12.7.1. Components of the NML system --
12.7.2. Clocking structures and dissipation by the clocking apparatus --
12.7.3. Novel methods of NML clocking --
12.7.4. Inputs and outputs --
12.8. Nanomagnet logic in perpendicular media Note continued: 12.8.1. Properties of magnetic multilayers with perpendicular anisotropy --
12.8.2. Clocking --
12.8.3. A full-adder benchmark structure --
12.9. Case study on two circuits --
12.10. The circuit paradigm in NML --
12.11. Outlook: the future of NML circuits --
Acknowledgments --
References --
13. Spin torque majority gate logic / George I. Bourianoff --
13.1. Introduction --
13.2. In-plane magnetization SMG --
13.3. Simulation model --
13.4. Patterns of in-plane magnetization switching --
13.5. Perpendicular magnetization SMG --
13.6. Patterns of perpendicular magnetization switching --
13.7. Conclusion --
References --
14. Spin wave phase logic / Alexander Khitun --
14.1. Introduction --
14.2. Computing with spin waves --
14.3. Experimentally-demonstrated spin wave components and devices --
14.4. Phase-based logic devices --
14.5. Spin wave-based logic circuits and architectures --
14.5.1. Logic circuits --
14.5.2. Architectures with spin wave buses --
14.6. Comparison with CMOS --
14.7. Summary --
References --
Section V Interconnect considerations --
15. Interconnect considerations / Azad Naeemi --
15.1. Introduction --
15.2. The interconnect problem --
15.2.1. The routing problem --
15.2.2. Interconnect problem from the resistance-capacitance perspective --
15.3. Interconnect options for emerging charge-based device technologies --
15.4. Interconnect considerations for spin circuits --
15.5. Spin relaxation mechanisms --
15.5.1. Spin relaxation in silicon --
15.5.2. Spin relaxation in gallium arsenide --
15.5.3. Spin relaxation in metals and graphene --
15.6. Spin injection and transport efficiency --
15.7. Comparison of electrical and semi-conducting spintronic interconnects --
15.8. Conclusion and outlook --
References.
Responsibility: Tsu-Jae King Liu, University of California, Berkeley ; Kelin Kuhn, Intel Corporation.

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