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Computer hardware description languages and their applications : proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL'93 sonsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993 Preview this item
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Computer hardware description languages and their applications : proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL'93 sonsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993

Author: David Agnew; Luc J M Claesen; Raul Camposano
Publisher: Amsterdam ; London : North-Holland, cop. 1993.
Series: IFIP transactions. Computer science and technology, A-32.
Edition/Format:   Print book : Conference publication : EnglishView all editions and formats
Database:WorldCat
Summary:

This research-oriented publication makes a contribution to further developments in the field of hardware description languages (HDLs). The text includes coverage of: BDD-based systems design and  Read more...

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Genre/Form: Congrès
Material Type: Conference publication
Document Type: Book
All Authors / Contributors: David Agnew; Luc J M Claesen; Raul Camposano
ISBN: 0444816410 9780444816412
OCLC Number: 490014489
Description: 1 vol. (XIV-604 p.) ; 22 cm
Contents: Part 1 Invited presentation: real time distributed systems, M.R. Barbacci. Part 2 BDD-based design and analysis techniques: verification of the futurebus + cache coherence protocol, E.M. Clarke et al; exploiting symbolic traversal techniques for efficient process algebra manipulation (PRAM), P. Camurati et al. Part 3 HDL-based design methods: HW/SW co-design with PRAMs using codes, K. Buchenrieder et al; prevail-DM - a framework-based environment for formal hardware verification, F.R. Wagner. Part 4 Synthesis and verification: a rewriting based method for the formal verification of microprocessors, M. Allemand; reasoning about the VHDL standard logic package signal data type, J.W. Gambles and P.J. Windley; an efficient data-path synthesis based on algorithmic description under the constraints of time and area, X.-J. Xu and M. Ishizuka. Part 5 Invited presentation: automatic verification of sequential circuit designs, E.M. Clarke. Part 6 Protocol specification: toward a basis for protocol specification and process decomposition, K. Rath and S.D. Johnson; integrating SDL and VHDL for system-level hardware design, W. Glunz et al. Part 7 Formal reasoning about regular structures: reasoning about array structures using a dependently typed logic, A. Dent and K. Hanna; VHDL description and formal verification of systolic multipliers, L. Pierre; transformational rewriting with ruby, R. Sharp and O. Rasmussen. Part 8 High level synthesis: a representation for the binding of RT-component functionality to HDL behavior, R.P. Ang and N.I. Dutt; performance specification and measurement, R. Mandayam and R. Vemuri. Part 9 VHDL: system-level specification and design using VHDL - a case study, W. Ecker and S. Marz; a denotational definition of the VHDL simulation kernel, K.C. Davis; checking DFT rules with a VHDL simulator, W. Glunz and T. Rossel; parameterized VHDL entities for the simulation of hybrid circuits, M. Ryba et al. (Part Contents).
Series Title: IFIP transactions. Computer science and technology, A-32.
Responsibility: edited by David Agnew, Luc Calaesen, Raul Camposano.

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