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Computer hardware description languages and their applications

Author: Mario R Barbacci; C J Koomen; International Federation for Information Processing.
Publisher: North-Holland, 1987.
Edition/Format:   Print book : Conference publication : EnglishView all editions and formats
Database:WorldCat
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Material Type: Conference publication
Document Type: Book
All Authors / Contributors: Mario R Barbacci; C J Koomen; International Federation for Information Processing.
ISBN: 0444702350 9780444702357
OCLC Number: 18747288
Description: 405 pages
Contents: Simulation I. HDL Modeling for Process Oriented Simulation (M. Roumeliotis, J.R. Armstrong). Hardware Description and Simulation Using Concurrent Prolog (D. Weinbaum, E. Shapiro). Program-Specific and Architecture-Specific Simulators (B. Siegell, T. Gross). Analysis. Logical Analysis of Digital Circuits (I. Gertner, R.P. Kurshan). Analysis of Behavioral DACAPO Descriptions (R. Bruck, R. Klomps, J. Schuetz). Functional Extraction from Personality Matrixes of MOL (Matrix-Oriented Logic) Circuits (J. Gebhard et al.). Design (Systems). EDIF Standard Supports Version Control in CAD Systems (E.R. Marx). An Animated Modelling Environment for Parallel Architectures (D.C.A. Bulterman). Simulation II. MIAKA: A Microassembler for the Register Transfer Language KARL II (H. Bassmann, Ph. W. Besslich). Functional Fault Model Generation for Fault Coverage Estimation of VLSI Designs Using Syntax Directed Techniques (G.M. Silberman, I. Spillinger). A Meta-Assembler for Creating the Simulation Files of the Instruction Set Processor Specifications (S. Dasgupta, M.H. Ozcanhan). Design (Methods). On the Plausibility of Architectural Designs (S. Dasgupta, U. Aguero). Design Criteria and Formal Description Techniques (M. Daniels). A Digital Systems Design Methodology Based on Nets of Agencies (F.R. Wagner, C.M.D. Freitas, L.G. Golendziner). Invited Paper. Formal Verification of Hardware Correctness: An Introduction (P. Camurati, P. Prinetto). Verification I. Two Techniques for Automating Firmware Design Verification (R. Beccard et al.). Specification and Verification of VLSI Systems Actional Behaviour (T. Larsson). Verification II. REX - Shifting Functional Design Verification Towards RT-Level by Automatic Register-Transfer-Net Extraction (R.W. Hartenstein, W. Nebel). Modelling and Verification of Digital Systems Using Temporal Logic (G. Venkatesh). Petri Net Models for the Description and Verification of Parallel Bus Protocols (P. Civera et al.). Languages. The MoDL Hardware Design System (J. Smit et al.). Modern Object-Oriented Programming Language as an HDL (A. Pawlak, W. Wrona). Hardware Description with Recursion Equations (J.T. O'Donnell). Invited Paper. Electronic Design Automation at a Glance (J.P. Mermet).
Responsibility: edited by M.R. Barbacci, C.J. Koomen.

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