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Design for high performance, low power, and reliable 3D integrated circuits

Autor: Sung Kyu Lim
Editorial: New York ; London : Springer, ©2013.
Edición/Formato:   Libro-e : Documento : Inglés (eng)Ver todas las ediciones y todos los formatos
Base de datos:WorldCat
Resumen:
This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous "manufacturing-ready" GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs. Coverage also includes various  Leer más
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Género/Forma: Electronic books
Formato físico adicional: Print version:
Lim, Sung Kyu.
Design for high performance, low power, and reliable 3D integrated circuits.
New York ; London : Springer, 2012
(OCoLC)819520313
Tipo de material: Documento, Recurso en Internet
Tipo de documento: Recurso en Internet, Archivo de computadora
Todos autores / colaboradores: Sung Kyu Lim
ISBN: 9781441995421 1441995420 1441995412 9781441995414
Número OCLC: 821614862
Descripción: 1 online resource (xxviii, 560 pages) : illustrations (some color)
Contenido: Regular vs Irregular TSV Placementfor 3D IC --
Steiner Routingfor 3D IC --
Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC --
Power Delivery Network Design for 3D IC --
3D Clock Routing for Pre-bond Testability --
TSV-to-TSV Coupling Analysis and Optimization --
TSV Current Crowding and Power Integrity --
Modeling of Atomic Concentration at the Wire-to-TSV Interface --
Multi-Objective Archetectural Floorplanning for 3D IC --
Thermal-aware Gate-level Placement for 3D IC --
3D IC Cooling with Micro-Fluidic Channels --
Mechanical Reliability Analysis and Optimization for 3D IC --
Impact of Mechanical Stress on Timing Variation for 3D IC --
Chip/Package Co-Analysis of Mechanical Stress for 3D IC --
3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations --
TSV Interfracial Crack Analysis and Optimization --
Ultra High Logic Designs Using Monolithic 3D Integration --
Impact of TSV Scaling on 3D IC Design Quality --
3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.
Responsabilidad: Sung Kyu Lim.
Más información:

Resumen:

This book describes a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It provides full details of  Leer más

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