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Digital logic design principles

Author: Norman Balabanian; Bradley Carlson
Publisher: New York : Wiley, ©2001.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

This book is an introduction on the principles of digital logic circuits. While providing coverage to the usual topics in combinational and sequential circuit principles, it also includes a chapter  Read more...

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Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Norman Balabanian; Bradley Carlson
ISBN: 0471293512 9780471293514
OCLC Number: 44972083
Description: xiii, 373 pages : illustrations ; 25 cm
Contents: Chapter 1. Number Representation, Codes, and Code Conversion 1 --
1. Systems: Digital and Analog 1 --
2. Hardware, Software, and Firmware 3 --
3. Number Systems 4 --
Binary and Other Number Systems 5 --
Base Conversions 7 --
Converting to the Decimal System 7 --
Converting from The Decimal System 7 --
From Octal or Hexadecimal to Binary 9 --
Binary Arithmetic 10 --
Addition 10 --
Subtraction 11 --
Multiplication 11 --
Division 11 --
Complements: Two's and One's 12 --
Addition of Binary Numbers 14 --
4. Codes and Code Conversion 17 --
Binary-Coded Decimal 18 --
Weighted Codes 18 --
Gray Code 19 --
Seven-Segment Code 20 --
Alphanumeric Codes 21 --
5. Error Detection and Correction 22 --
Error-Detecting Codes 22 --
Error-Correcting Codes 24 --
Hamming Codes 25 --
Chapter 2. Switching Algebra and Logic Gates 34 --
1. Boolean Algebra 34 --
Duality Principle 36 --
Fundamental Theorems 36 --
Switching Algebra 39 --
2. Switching Operations 41 --
AND Operation 41 --
OR Operation 41 --
NOT Operation 42 --
3. Switching Expressions 43 --
Minterms, Maxterms, and Canonic Forms 44 --
Generalization of De Morgan's Law 46 --
4. Switching Functions 48 --
Switching Operations on Switching Functions 49 --
Number of Terms in Canonic Forms 50 --
Shannon's Expansion Theorem 51 --
Sum-of-Products Form 51 --
Product-of-Sums Form 52 --
5. Other Switching Operations 53 --
Exclusive OR 53 --
NAND, NOR, and XNOR Operations 54 --
6. Universal Sets of Operations 54 --
7. Logic Gates 56 --
Alternative Forms of NAND and NOR Gates 57 --
Exclusive-OR Gates 58 --
8. Positive, Negative, and Mixed Logic 59 --
9. Some Practical Matters Regarding Gates 61 --
Logic Families 62 --
Input/Output Characteristics of Logic Gates 63 --
Fan-out and Fan-in 67 --
Buffers 67 --
Power Consumption 68 --
Noise Margin 68 --
Speed and Propagation Delay 69 --
10. Integrated Circuits 70 --
Some Characteristics of ICs 71 --
Design Economy 73 --
Application-Specific ICs 74 --
11. Wired Logic 74 --
Tristate (High-Impedance) Logic Gates 74 --
Open-Collector and Open-Drain Logic Gates 75 --
Chapter 3. Representation and Implementation of Logic Functions 81 --
1. Minterm and Maxterm Lists 81 --
Minterm Lists and Sum-of-Products Form 82 --
Maxterm Lists and Product-of-Sums Form 83 --
2. Logic Maps 84 --
Logical Adjacency and Geometrical Adjacency 84 --
Cubes of Order k 89 --
3. Minimal Realizations of Switching Functions 92 --
Irreducible and Minimal Expressions 92 --
Prime Implicants 93 --
Minimal Sum-of-Products Expressions 95 --
Minimal Product-of-Sums Expressions 97 --
Two-Level Implementations 98 --
AND-OR Implementation 98 --
NAND Implementation 99 --
OR-AND Implementation 100 --
4. Implementation of Logic Expressions 101 --
Analysis 103 --
Features of Gate Circuits 104 --
5. Timing Diagrams 105 --
6. Incompletely Specified Functions 107 --
Don't-Cares 107 --
7. Comparators 109 --
2-Bit Comparators 109 --
Generalization 111 --
4-Bit Comparators 111 --
Comparators of Even Numbers of Bits 112 --
Comparators of Odd Numbers of Bits 112 --
8. Prime Implicant Determination: Tabular Method 112 --
Representations of Adjacent k-Cubes 113 --
Ranking by Index 114 --
Incompletely Specified Functions 116 --
Selection of a Minimal Expression 117 --
Completely Specified Functions 117 --
Handling Don't-Cares 119 --
9. Multiple-Output Circuits 119 --
Chapter 4. Combinational Logic Design 132 --
1. Binary Adders 132 --
Full Adder 133 --
Ripple-Carry Adder 135 --
Carry-Lookahead Adder 136 --
Binary Subtractor 140 --
Two's-Complement Adder and Subtractor 140 --
One's-Complement Adder and Subtractor 141 --
2. Multiplexers 142 --
Multiplexers as General-Purpose Logic Circuits 145 --
3. Decoders and Encoders 147 --
Demultiplexers 147 --c n-to-2n-Line Decoder 149 --
Tree Decoder 150 --
Decoders as General-Purpose Logic Circuits: Code Conversion 150 --
4. Read-Only Memory (ROM) 152 --
5. Other LSI Programmable Logic Devices 155 --
Programmed Logic Array (PLA) 155 --
Programmed Array Logic (PAL) 157 --
Chapter 5. Sequential Circuit Components 168 --
1. Definitions and Basic Concepts 168 --
2. Latches and Flip-Flops 172 --
SR Latch 172 --
Timing Problems and Clocked SR Latches 176 --
JK Latch 177 --
Master-Slave Latch 178 --
A Possible Design 179 --
An Alternative Master-Slave Design 180 --
Edge-Triggering Parameters 181 --
Delay (D) Flip-Flops 182 --
Edge-Triggered D Flip-Flop 182 --
T Flip-Flop 184 --
Flip-Flop Excitation Requirements 185 --
3. Registers 186 --
Serial-Load Shift Register 187 --
Parallel-Load Shift Register 188 --
Parallel-to-Serial Conversion 189 --
Universal Registers 190 --
Chapter 6. Synchronous Sequential Machines 198 --
State Diagram 200 --
State Table 203 --
Constructing a State Table from a State Diagram 203 --
2. State Assignments 206 --
Analysis 208 --
Rules of Thumb for Assigning States 209 --
3. General Design Procedure 213 --
Mealy Machine 213 --
Moore Machine 218 --
4. State Equivalence and Machine Minimization 219 --
Distinguishability and Equivalence 220 --
Machine Minimization 221 --
5. Machines with Finite Memory Spans 223 --
Machines with Finite Input Memory 224 --
Machines with Finite Output Memory 225 --
Finite-Memory Machines 227 --
6. Synchronous Counters 227 --
Single-Mode Counters 228 --
Unit-Distance Counters 228 --
Ring Counters 230 --
Hang-up States 231 --
Multimode Counters 232 --
Modulo-6 Up-Down Counter 232 --
7. Algorithmic State Machines 233 --
Basic Principles 234 --
8. Asynchronous Inputs 238 --
Asynchronous Communication (Handshaking) 239 --
Chapter 7. Asynchronous Sequential Machines 254 --
1. Fundamental-Mode Model 255 --
2. Flow Table 256 --
Primitive Flow Tables 256 --
Assigning Outputs to Unstable States 260 --
3. Reduction of Incompletely Specified Machines 261 --
Merger Table 262 --
Compatibility 262 --
Construction of the Merger Table 263 --
Determination of Minimal, Closed Covers 265 --
Transition Tables 267 --
4. Races and Cycles 270 --
Critical and Noncritical Races 271 --
Cycles and Oscillations 273 --
5. Hazards 275 --
Static Hazards 275 --
Dynamic Hazards 280 --
Essential Hazards 280 --
Chapter 8. Design Using Hardware Description Languages 290 --
1. Hardware Description Language ABEL 291 --
Adder Specification in ABEL 292 --
Behavioral versus Operational Description 294 --
Adder Specification in ABEL 296 --
Sequential Circuit Specification in ABEL 297 --
Don't-Care Conditions in ABEL 300 --
Hierarchical Specifications in ABEL 301 --
2. Programmable Logic Devices (PLDs) 306 --
Complex Programmable Logic Devices 310 --
Field-Programmable Gate Arrays 315 --
3. Design Flow for HDL Specifications 317 --
Synthesis and Technology Mapping of ABEL Specifications 318 --
Simulation of ABEL Specifications 321 --
Chapter 9. Computer Organization 325 --
1. Control and Datapath Units of a Processor 325 --
Datapath Unit 326 --
Control Unit 327 --
Serial Multiplier Example 327 --
2. Basic Stored-Program Computer 334 --
Central Processing Unit (CPU) 335 --
Simple Datapath 335 --
Controlling the Simple Datapath 338 --
3. Control-Unit Implementations 340 --
Hard-Wired Control Unit 340 --
Memory and I/O Interface 342 --
Micro-Programmed Control Unit 343 --
4. Contemporary Microprocessor Architectures 347 --
Instruction Pipelining 347 --
Parallel Hardware Units 349 --
Memory Hierarchy 350 --
Complex Instruction Set Computer (CISC) 350 --
Reduced Instruction Set Computer (RISC) 352 --
5. Microcontroller Architectures 353 --
Appendix MOSFETS and Bipolar Junction Transistors 357.
Responsibility: Norman Balabanian, Bradley Carlson.
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