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Digital system verification : a combined formal methods and simulation framework

Author: Lun Li; Mitchell Aaron Thornton
Publisher: [San Rafael, Calif.] : Morgan & Claypool Publishers, ©2010.
Series: Synthesis lectures on digital circuits and systems, #27.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques.  Read more...
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Details

Genre/Form: Electronic books
Additional Physical Format: Print version:
Li, Lun, 1970-
Digital system verification.
[San Rafael, Calif.] : Morgan & Claypool Publishers, ©2010
(OCoLC)588869825
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Lun Li; Mitchell Aaron Thornton
ISBN: 9781608451791 1608451798
OCLC Number: 588869825
Description: 1 online resource (xiv, 79 pages) : illustrations.
Contents: 1. Introduction --
2. Formal methods background --
Existing techniques for verification --
Equivalence checking --
Model checking --
Bounded model checking --
Fundamental data structures and algorithms --
Boolean functions and finite state machines --
Image computation using the transition relation --
Symbolic FSM state space traversal --
Binary decision diagrams --
The Boolean satisfiability problem --
Image computation --
BDD-based approach --
SAT based methods --
Hybrid approaches --
A genetic algorithm approach for the BDD-based method --
Combing BDD and SAT in one framework --
Summary.
Series Title: Synthesis lectures on digital circuits and systems, #27.
Responsibility: Lun Li, Mitchell A. Thornton.

Abstract:

Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative. This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation.

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