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Digital systems testing and testable design

Author: Miron Abramovici; Melvin A Breuer; Arthur D Friedman
Publisher: New York, NY : IEEE ; Hoboken, New Jersey : Wiley-Interscience, [1994] ©1990
Edition/Format:   eBook : Document : English : Revised PrintingView all editions and formats
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Additional Physical Format: Print version:
Abramovici, Miron.
Digital systems testing and testable design.
New York : IEEE Press, [1994], ©1990
(DLC) 94233953
(OCoLC)36590141
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Miron Abramovici; Melvin A Breuer; Arthur D Friedman
ISBN: 9780470544389 0470544384
OCLC Number: 557402292
Notes: "This is the IEEE revised printing of the book previously published by W. H. Freeman and Company in 1990 under the title Digital Systems Testing and Testable Design."--Title page verso.
Description: 1 online resource (xxii, 652 pages) : illustrations
Contents: 1. INTRODUCTION --
2. MODELING. 2.1. Basic Concepts. 2.2. Functional Modeling at the Logic Level. 2.3. Functional Modeling at the Register Level. 2.4. Structural Models. 2.5. Level of Modeling --
3. LOGIC SIMULATION. 3.1. Applications. 3.2. Problems in Simulation-Based Design Verification. 3.3. Types of Simulation. 3.4. The Unknown Logic Value. 3.5. Compiled Simulation. 3.6. Event-Driven Simulation. 3.7. Delay Models. 3.8. Element Evaluation. 3.9. Hazard Detection. 3.10. Gate-Level Event-Driven Simulation. 3.11. Simulation Engines --
4. FAULT MODELING. 4.1. Logical Fault Models. 4.2. Fault Detection and Redundancy. 4.3. Fault Equivalence and Fault Location. 4.4. Fault Dominance. 4.5. The Single Stuck-Fault Model. 4.6. The Multiple Stuck-Fault Model. 4.7. Stuck RTL Variables. 4.8. Fault Variables --
5. FAULT SIMULATION. 5.1. Applications. 5.2. General Fault Simulation Techniques. 5.3. Fault Simulation for Combinational Circuits. 5.4. Fault Sampling. 5.5. Statistical Fault Analysis. 5.6. Concluding Remarks --
6. TESTING FOR SINGLE STUCK FAULTS 181. 6.1. Basic Issues. 6.2. ATG for SSFs in Combinational Circuits. 6.3. ATG for SSFs in Sequential Circuits. 6.4. Concluding Remarks --
7. TESTING FOR BRIDGING FAULTS. 7.1. The Bridging-Fault Model. 7.2. Detection of Nonfeedback Bridging Faults. 7.3. Detection of Feedback Bridging Faults. 7.4. Bridging Faults Simulation. 7.5. Test Generation for Bridging Faults. 7.6. Concluding Remarks --
8. FUNCTIONAL TESTING. 8.1. Basic Issues. 8.2. Functional Testing Without Fault Models. 8.3. Exhaustive and Pseudoexhaustive Testing. 8.4. Functional Testing with Specific Fault Models. 8.5. Concluding Remarks --
9. DESIGN FOR TESTABILITY. 9.1. Testability. 9.2. Ad Hoc Design for Testability Techniques. 9.3. Controllability and Observability by Means of Scan Registers. 9.4. Generic Scan-Based Designs. 9.5. Storage Cells for Scan Designs. 9.6. Classical Scan Designs. 9.7. Scan Design Costs. 9.8. Board-Level and System-Level DFf Approaches. 9.9. Some Advanced Scan Concepts. 9.10. Boundary Scan Standards --
10. COMPRESSION TECHNIQUES. 10.1. General Aspects of Compression Techniques. 10.2. Ones-Count Compression. 10.3. Transition-Count Compression. 10.4. Parity-Check Compression. 10.5. Syndrome Testing. 10.6. Signature Analysis. 10.7. Concluding Remarks --
11. BUILT-IN SELF-TEST. 11.1. Introduction to BIST Concepts. 11.2. Test-Pattern Generation for BIST. 11.3. Generic Off-Line BIST Architectures. 11.4. Specific BIST Architectures. 11.5. Some Advanced BIST Concepts. 11.6. Design for Self-Test at Board Level --
12. LOGIC-LEVEL DIAGNOSIS. 12.1. Basic Concepts. 12.2. Fault Dictionary. 12.3. Guided-Probe Testing. 12.4. Diagnosis by UUT Reduction. 12.5. Fault Diagnosis for Combinational Circuits. 12.6. Expert Systems for Diagnosis. 12.7. Effect-Cause Analysis. 12.8. Diagnostic Reasoning Based on Structure and Behavior --
13. SELF-CHECKING DESIGN. 13.1. Basic Concepts. 13.2. Application of Error-Detecting and Error-Correcting Codes. 13.3. Multiple-Bit Errors. 13.4. Checking Circuits and Self-Checking. 13.5. Self-Checking Checkers. 13.6. Parity-Check Function. 13.7. Totally SelfChecking m/n Code Checkers. 13.8. Totally Self-Checking Equality Checkers. 13.9. Self-Checking Berger Code Checkers. 13.10. Toward a General Theory of Self-Checking Combinational Circuits. 13.11. Self-Checking Sequential Circuits --
14. PLA TESTING. 14.1. Introduction. 14.2. PLA Testing Problems. 14.3. Test Generation Algorithms for PLAs. 14.4. Testable PLA Designs. 14.5. Evaluation of PLA Test Methodologies --
15. SYSTEM-LEVEL DIAGNOSIS. 15.1. A Simple Model of System-Level Diagnosis. 15.2. Generalizations of the PMC Model.
Responsibility: Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman.
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