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Embedded system design : topics, techniques, and trends : IFIP TC10 Working Conference--International Embedded Systems Symposium (IESS) : May 30-June 1, 2007, Irvine (CA), USA
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Embedded system design : topics, techniques, and trends : IFIP TC10 Working Conference--International Embedded Systems Symposium (IESS) : May 30-June 1, 2007, Irvine (CA), USA

Author: Achim Rettberg; et al
Publisher: New York : Springer, 2007.
Series: International Federation for Information Processing (Series), 231.
Edition/Format:   eBook : Document : Conference publication : English
Summary:

Presents the technical program of the 2007 International Embedded Systems Symposium held in Irvine, California. This book covers techniques and trends in embedded system design, including design  Read more...

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Genre/Form: Congresses
Additional Physical Format: IESS'07 (2007 : Irvine, Calif.)
Embedded system design : topics, techniques, and trends : IFIP TC10 Working Conference--International Embedded Systems Symposium (IESS) : May 30-June 1, 2007, Irvine (CA), USA
(OCoLC)166291462
Material Type: Conference publication, Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Achim Rettberg; et al
ISBN: 9780387722573 0387722572 0387722580 9780387722580 9786610864560 661086456X
OCLC Number: 516040590
Description: 1 online resource (xvi, 444 p.) : ill.
Contents: Requirements and Concepts for Transaction Level Assertion Refinement.- Run-Time Efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities.- Automotive System Optimization Using Sensitivity Analysis.- Towards Dynamic Load Balancing for Distributed Embedded Automotive Systems.- Automatic Data Path Generation from C code for Custom Processors.- An Interactive Design Environment for C-based High-Level Synthesis.- Embedded Vertex Shader in FPGA.- An Interactive Model Re-Coder for Efficient SoC Specification.- Smart Speed Technology.- Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints.- Data Reuse Driven Memory and Network-On-Chip Co-Synthesis.- Hardware Implementation of the Time-Triggered Ethernet Controller.- Generic Architecture Designed for Biomedical Embedded Systems.- Reconfigurable Hardware for Optimizing Workflows in Networked Nodes.-Configurable Medium Access Control for Wireless Sensor Networks.- Modeling of Software-Hardware Complexes.- Modeling of Software-Hardware Complexes.- Enhancing a Real-Time Distributed Computing Component Model through Cross-Fertilization.- Medical Embedded Systems.
Series Title: International Federation for Information Processing (Series), 231.
Responsibility: edited by Achim Rettberg ... [et al.].

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