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ESD. Design and synthesis

Author: Steven H Voldman
Publisher: Chichester, West Sussex, U.K. : Wiley, 2011.
Series: ESD series.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:
"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the
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Document Type: Book
All Authors / Contributors: Steven H Voldman
ISBN: 9780470685716 0470685719 9781119991144 1119991145 9781119991137 1119991137 9781119992653 1119992656
OCLC Number: 682892492
Description: xx, 270 pages : illustrations ; 25 cm.
Contents: Machine generated contents note: 1. ESD Design Synthesis --
1.1. ESD Design Synthesis and Architecture Flow --
1.1.1. Top-Down ESD Design --
1.1.2. Bottom-Up ESD Design --
1.1.3. Top-Down ESD Design --
Memory Semiconductor Chips --
1.1.4. Top-Down ESD Design --
ASIC Design System --
1.2. ESD Design --
The Signal Path and the Alternate Current Path --
1.3. ESD Electrical Circuit and Schematic Architecture Concepts --
1.3.1. The Ideal ESD Network and the Current --
Voltage DC Design Window --
1.3.2. The ESD Design Window --
1.3.3. The Ideal ESD Networks in the Frequency Domain Design Window --
1.4. Mapping Semiconductor Chips and ESD Designs --
1.4.1. Mapping Across Semiconductor Fabricators --
1.4.2. ESD Design Mapping Across Technology Generations --
1.4.3. Mapping from Bipolar Technology to CMOS Technology --
1.4.4. Mapping from Digital CMOS Technology to Mixed Signal Analog --
Digital CMOS Technology --
1.4.5. Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI) --
1.4.6. ESD Design --
Mapping CMOS to RF CMOS Technology. 1.5. ESD Chip Architecture and ESD Test Standards --
1.5.1. ESD Chip Architecture and ESD Testing --
1.6. ESD Testing --
1.6.1. ESD Qualification Testing --
1.6.2. ESD Test Models --
1.6.3. ESD Characterization Testing --
1.6.4. TLP Testing --
1.7. ESD Chip Architecture and ESD Alternative Current Paths --
1.7.1. ESD Circuits, I/O, and Cores --
1.7.2. ESD Signal Pin Circuits --
1.7.3. ESD Power Clamp Networks --
1.7.4. ESD Rail-to-Rail Circuits --
1.7.5. ESD Design and Noise --
1.7.6. Internal Signal Path ESD Networks --
1.7.7. Cross-Domain ESD Networks --
1.8. ESD Networks, Sequencing, and Chip Architecture --
1.9. ESD Design Synthesis --
Latchup-Free ESD Networks --
1.10. ESD Design Concepts --
Buffering --
Inter-Device --
1.11. ESD Design Concepts --
Ballasting --
Inter-Device --
1.12. ESD Design Concepts --
Ballasting --
Intra-Device --
1.13. ESD Design Concepts --
Distributed Load Techniques --
1.14. ESD Design Concepts --
Dummy Circuits --
1.15. ESD Design Concepts --
Power Supply De-Coupling --
1.16. ESD Design Concepts --
Feedback Loop De-Coupling --
1.17. ESD Layout and Floorplan-Related Concepts. 1.17.1. Design Symmetry --
1.17.2. Design Segmentation --
1.17.3. ESD Design Concepts --
Utilization of Empty Space --
1.17.4. ESD Design Synthesis --
Across Chip Line Width Variation (ACLV) --
1.17.5. ESD Design Concepts --
Dummy Shapes --
1.17.6. ESD Design Concepts --
Dummy Masks --
1.17.7. ESD Design Concepts --
Adjacency --
1.18. ESD Design Concepts --
Analog Circuit Techniques --
1.19. ESD Design Concepts --
Wire Bonds --
1.20. Design Rules --
1.20.1. ESD Design Rule Checking (DRC) --
1.20.2. ESD Layout vs. Schematic (LVS) --
1.20.3. Electrical Resistance Checking (ERC) --
1.21. Summary and Closing Comments --
Problems --
References --
2. ESD Architecture and Floorplanning --
2.1. ESD Design Floorplan --
2.2. Peripheral I/O Design --
2.2.1. Pad-Limited Peripheral I/O Design Architecture --
2.2.2. Pad-Limited Peripheral I/O Design Architecture --
Staggered I/O --
2.2.3. Core-Limited Peripheral I/O Design Architecture --
2.3. Lumped ESD Power Clamp in Peripheral I/O Design Architecture --
2.3.1. Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners. 2.3.2. Lumped ESD Power Clamp in Peripheral I/O Design Architecture --
Power Pads --
2.4. Lumped ESD Power Clamp in Peripheral I/O Design Architecture --
Master/Slave ESD Power Clamp System --
2.5. Array I/O --
2.5.1. Array I/O --
Off-Chip Driver Banks --
2.5.2. Array I/O Nibble Architecture --
2.5.3. Array I/O Pair Architecture --
2.5.4. Array I/O --
Fully Distributed --
2.6. ESD Architecture --
Dummy Bus Architectures --
2.6.1. ESD Architecture --
Dummy VDD Bus --
2.6.2. ESD Architecture --
Dummy Ground (VSS) Bus --
2.7. Native Voltage Power Supply Architecture --
2.7.1. Single Power Supply Architecture --
2.8. Mixed-Voltage Architecture --
2.8.1. Mixed-Voltage Architecture --
Single Power Supply --
2.8.2. Mixed-Voltage Architecture --
Dual Power Supply --
2.9. Mixed-Signal Architecture --
2.9.1. Mixed-Signal Architecture --
Bipolar --
2.9.2. Mixed-Signal Architecture --
CMOS --
2.10. Mixed-System Architecture --
Digital and Analog CMOS --
2.10.1. Digital and Analog CMOS Architecture --
2.10.2. Digital and Analog Floorplan --
Placement of Analog Circuits --
2.11. Mixed-Signal Architecture --
Digital, Analog, and RF Architecture. 2.12. Summary and Closing Comments --
Problems --
References --
3. ESD Power Grid Design --
3.1. ESD Power Grid --
3.1.1. ESD Power Grid --
Key ESD Design Parameters --
3.1.2. ESD and the Alternative Current Path --
The Role of ESD Power Grid Resistance --
3.2. Semiconductor Chip Impedance --
3.3. Interconnect Failure and Dynamic On-Resistance --
3.3.1. Interconnect Dynamic On-Resistance --
3.3.2. Ti/Al/Ti Interconnect Failure --
3.3.3. Copper Interconnect Failure --
3.3.4. Melting Temperature of Interconnect Materials --
3.4. Interconnect Wire and Via Guidelines --
3.4.1. Interconnect Wire and Via Guidelines for HBM ESD Events --
3.4.2. Interconnect Wire and Via Guidelines for MM ESD Events --
3.4.3. Interconnect Wire and Via Guidelines for CDM ESD Events --
3.4.4. Interconnect Wire and Via Guidelines for HMM and IEC 61000-4-2 ESD Events --
3.4.5. Wire and Via ESD Metrics --
3.5. ESD Power Grid Resistance --
3.5.1. Power Grid Design --
ESD Input to Power Grid Resistance --
3.5.2. ESD Input to Power Grid Connections --
Across ESD Bus Resistance --
3.5.3. Power Grid Design --
ESD Power Clamp to Power Grid Resistance Evaluation. 3.5.4. Power Grid Design --
Resistance Evaluation --
3.5.5. Power Grid Design Distribution Representation --
3.6. Power Grid Layout Design --
3.6.1. Power Grid Design --
Slotting of Power Grid --
3.6.2. Power Grid Design --
Segmentation of Power Grids --
3.6.3. Power Grid Design --
Chip Corners --
3.6.4. Power Grid Design --
Stacking of Metal Levels --
3.6.5. Power Grid Design --
Wiring Bays and Weaved Power Bus Designs --
3.7. ESD Specification Power Grid Considerations --
3.7.1. CDM Specification Power Grid and Interconnect Design Considerations --
3.7.2. HMM and IEC Specification Power Grid and Interconnect Design Considerations --
3.8. Power Grid Design Synthesis --
ESD Design Rule Checking Methods --
3.8.1. Power Grid Design Synthesis --
ESD DRC Methods Using an ESD Virtual Design Level --
3.8.2. Power Grid Design Synthesis --
ESD DRC Methods Using an ESD Interconnect Parameterized Cell --
3.9. Summary and Closing Comments --
Problems --
References --
4. ESD Power Clamps --
4.1. ESD Power Clamps --
4.1.1. Classification of ESD Power Clamps --
4.1.2. Design Synthesis of ESD Power Clamp --
Key Design Parameters. 4.2. Design Synthesis of ESD Power Clamps --
4.2.1. Transient Response Frequency Trigger Element and the ESD Frequency Window --
4.2.2. The ESD Power Clamp Frequency Design Window --
4.2.3. Design Synthesis of ESD Power Clamp --
Voltage Triggered ESD Trigger Elements --
4.3. Design Synthesis of ESD Power Clamp --
The ESD Power Clamp Shunting Element --
4.3.1. ESD Power Clamp Trigger Condition vs. Shunt Failure --
4.3.2. ESD Clamp Element --
Width Scaling --
4.3.3. ESD Clamp Element --
On-Resistance --
4.3.4. ESD Clamp Element --
Safe Operating Area --
4.4. ESD Power Clamp Issues --
4.4.1. ESD Power Clamp Issues --
Power-Up and Power-Down --
4.4.2. ESD Power Clamp Issues --
False Triggering --
4.4.3. ESD Power Clamp Issues --
Pre-Charging --
4.4.4. ESD Power Clamp Issues --
Post-Charging --
4.5. ESD Power Clamp Design --
4.5.1. Native Power Supply RC-Triggered MOSFET ESD Power Clamp --
4.5.2. Non-Native Power Supply RC-Triggered MOSFET ESD Power Clamp --
4.5.3. ESD Power Clamp Networks with Improved Inverter Stage Feedback --
4.5.4. ESD Power Clamp Design Synthesis --
Forward Bias Triggered ESD Power Clamps. 4.5.5. ESD Power Clamp Design Synthesis --
IEC 61000-4-2 Responsive ESD Power Clamps --
4.5.6. ESD Power Clamp Design Synthesis --
Pre-Charging and Post-Charging Insensitive ESD Power Clamps --
4.6. ESD Power Clamp Design Synthesis --
Bipolar ESD Power Clamps --
4.6.1. Bipolar ESD Power Clamps with Zener Breakdown Trigger Element --
4.6.2. Bipolar ESD Power Clamps with Bipolar Transistor BVceo Breakdown Trigger Element --
4.6.3. Bipolar ESD Power Clamps with BVceo Bipolar Transistor Trigger and Variable Trigger Diode String Network --
4.6.4. Bipolar ESD Power Clamps with Frequency Trigger Elements --
4.7. Master/Slave ESD Power Clamp Systems --
4.8. Summary and Closing Comments --
Problems --
References --
5. ESD Signal Pin Networks Design and Synthesis --
5.1. ESD Signal Pin Structures --
5.1.1. Classification of ESD Signal Pin Networks --
5.1.2. ESD Design Synthesis of ESD Signal Devices --
Key Design Parameters --
5.2. ESD Input Structures --
ESD and Bond Pads Layout --
5.2.1. ESD and Bond Pad Layout and Synthesis --
5.2.2. ESD Structures Between Bond Pads. 5.2.3. Split I/O and Bond Pad --
5.2.4. Split ESD Adjacent to Bond Pad --
5.2.5. ESD Structures Partially Under Bond Pads --
5.2.6. ESD Structures Under and Between the Bond Pads --
5.2.7. ESD Circuits and RF Bond Pad Integration --
5.2.8. RF ESD Signal Pad Structures Under Bond Pads --
5.3. ESD Design Synthesis and Layout of MOSFETs --
5.3.1. MOSFET Key Design Parameters --
5.3.2. Single MOSFET with Silicide Block Masks --
5.3.3. Series Cascode MOSFET --
5.3.4. Triple-well MOSFETs. 5.4. ESD Design Synthesis and Layout of Diodes --
5.4.1. ESD Diode Key Design Parameters --
5.4.2. ESD Design Synthesis of Dual-Diode Networks --
5.4.3. ESD Design Synthesis of Diode String Networks --
5.4.4. ESD Design Synthesis of Back-to-Back Diode String --
5.4.5. ESD Design Synthesis for Differential Pair --
5.5. ESD Design Synthesis of SCRs --
5.5.1. ESD Design Synthesis of Uni-directional SCRs --
5.5.2. ESD Design Synthesis of Bi-directional SCRs --
5.5.3. ESD Design Synthesis of SCRs --
External Trigger Element --
5.6. ESD Design Synthesis and Layout of Resistors --
5.6.1. Polysilicon Resistor Design Layout --
5.6.2. Diffusion Resistor Design Layout --
5.6.3. P-diffusion Resistor Design Layout --
5.6.4. N-diffusion Resistor Design --
5.6.5. Buried Resistors --
5.6.6. N-well Resistors --
5.7. ESD Design Synthesis of Inductors. 5.8. Summary and Closing Comments --
Problems --
References --
6. Guard Ring Design and Synthesis --
6.1. Guard Ring Design and Integration --
6.2. Guard Ring Characterization --
6.2.1. Guard Ring Efficiency --
6.2.2. Guard Ring Theory --
A Generalized Bipolar Transistor Perspective --
6.2.3. Guard Ring Theory --
A Probability of Escape Perspective --
6.2.4. Guard Ring --
The Injection Ratio --
6.3. Semiconductor Chip Guard Ring Seal --
6.4. I/O to Core Guard Rings --
6.5. I/O to I/O Guard Rings --
6.6. Within I/O Guard Rings --
6.6.1. Within I/O Cell Guard Ring --
6.6.2. ESD-to-I/O OCD Guard Ring --
6.7. ESD Signal Pin Guard Rings --
6.7.1. ESD Signal Pin Guard Rings and Dual-Diode ESD Network --
6.8. Library Element Guard Rings --
6.8.1. N-channel MOSFET Guard Rings --
6.8.2. P-channel MOSFET Guard Rings --
6.8.3. RF Guard Rings --
6.9. Mixed-Signal Guard Rings --
Digital to Analog --
6.10. Mixed-Voltage Guard Rings --
High Voltage to Low Voltage. 6.10.1. Guard Rings --
High Voltage --
6.11. Passive and Active Guard Rings --
6.11.1. Passive Guard Rings --
6.11.2. Active Guard Rings --
6.12. Trench Guard Rings --
6.13. TSV Guard Rings --
6.14. Guard Ring DRC --
6.14.1. Internal Latchup and Guard Ring Design Rules --
6.14.2. External Latchup Guard Ring Design Rules --
6.15. Guard Rings and Computer Aided Design Methods --
6.15.1. Built-in Guard Rings --
6.15.2. Guard Ring Parameterized Cells --
6.15.3. Guard Ring p-Cell SKILL Code --
6.15.4. Guard Ring Resistance CAD Design Checking --
6.15.5. Post-Processing Methodology of Guard Ring Modification --
6.16. Summary and Closing Comments --
Problems --
References --
7. ESD Full-Chip Design Integration and Architecture --
7.1. Design Synthesis and Integration --
7.2. Digital Design --
7.3. Custom Design vs. Standard Cell Design --
7.4. Memory ESD Design --
7.4.1. DRAM Design --
7.4.2. SRAM Design --
7.4.3. Non-Volatile RAM ESD Design --
7.5. Microprocessor ESD Design. 7.5.1. 3.3 V Microprocessor with 5.0 V to 3.3 V Interface --
7.5.2. 2.5 V Microprocessor with 5.0 V to 2.5 V Interface --
7.5.3. 1.8 V Microprocessor with 3.3 V to 1.8 V Interface --
7.6. Application-Specific Integrated Circuits --
7.6.1. ASIC ESD Design --
7.6.2. ASIC Design Gate Array Standard Cell I/O --
7.6.3. ASIC Design System with Multiple Power Rails --
7.6.4. ASIC Design System with Voltage Islands --
7.7. CMOS Image Processing Chip Design --
7.7.1. CMOS Image Processing Chip Design with Long/Narrow Standard Cell --
7.7.2. CMOS Image Processing Chip Design with Short/Wide Standard Cell --
7.8. Mixed-Signal Architecture --
7.8.1. Mixed-Signal Architecture --
Digital and Analog --
7.8.2. Mixed-Signal Architecture --
Digital, Analog, and RF --
7.9. Summary and Closing Comments --
Problems --
References.
Series Title: ESD series.
Responsibility: Steven H. Voldman.

Abstract:

Focused on fundamentals of ESD design to construct and integrate a semiconductor chip, this book enables ESD engineers to build better products by exploring the areas of ESD design synthesis, I/O  Read more...

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