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Fault-tolerance techniques for SRAM-based FPGAs

Author: Fernanda Lima Kastensmidt; Luigi Carro; Ricardo A L Reis
Publisher: Dordrecht : Springer, 2006.
Series: Frontiers in electronic testing, 32.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Database:WorldCat
Summary:

Reviews fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs), outlining many methods for designing fault tolerance systems. This title helps the reader choose the best  Read more...

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Genre/Form: Electronic books
Additional Physical Format: Print version:
Kastensmidt, Fernanda Lima.
Fault-tolerance techniques for SRAM-based FPGAs.
Dordrecht : Springer, 2006
(DLC) 2007270463
(OCoLC)69105498
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Fernanda Lima Kastensmidt; Luigi Carro; Ricardo A L Reis
ISBN: 9780387310695 038731069X 0387310681 9780387310688
OCLC Number: 209920029
Description: 1 online resource (xv, 183 p.) : ill.
Contents: DEDICATION. CONTRIBUTING AUTHORS. PREFACE. 1. INTRODUCTION. 2. RADIATION EFFECTS IN INTEGRATED CIRCUITS. 2.1 RADIATION ENVIROMENT OVERVIEW. 2.2 RADIATION EFFECTS IN INTEGRATED CIRCUITS. 2.2.1 SEU Classification. 2.3 PECULIAR EFFECTS IN SRAM-BASED FPGAS. 3. SINGLE EVENT UPSET (SEU) MITIGATION TECHNIQUES. 3.1 DESIGN-BASED TECHNIQUES. 3.1.1 Detection Techniques. 3.1.2 Mitigation Techniques. 3.1.2.1 Full Time and Hardware Redundancy. 3.1.2.2 Error Correction and Detection Codes. 3.1.2.3 Hardened Memory Cells. 3.2 EXAMPLES OF SEU MITIGATION TECHNIQUES IN ASICS. 3.3 EXAMPLES OF SEU MITIGATION TECHNIQUES IN FPGAS. 3.3.1 Antifuse based FPGAs. 3.3.2 SRAM-based FPGAs. 3.3.2.1 SEU Mitigation Solution in high-level description. 3.3.2.2 SEU Mitigation Solutions at the Architectural level. 3.3.2.3 Recovery technique. 4. ARCHITECTURAL SEU MITIGATION TECHNIQUES. 5. HIGH-LEVEL SEU MITIGATION TECHNIQUES. 5.1 TRIPLE MODULAR REDUNDANCY TECHNIQUE FOR FPGAS. 5.2 SCRUBBING. 6. TRIPLE MODULAR REDUNDANCY (TMR) ROBUSTNESS. 6.1 TEST DESIGN METHODOLOGY. 6.2 FAULT INJECTION IN THE FPGA BITSTREAM. 6.3 LOCATING THE UPSET IN THE DESIGN FLOORPLANNING. 6.3.1 Bit column location in the matrix. 6.3.2 Bit row location in the matrix. 6.3.3 Bit location in the CLB. 6.3.4 Bit Classification. 6.4 FAULT INJECTION RESULTS. 6.5 THE 'GOLDEN' CHIP APPROACH. 7. DESIGNING AND TESTING A TMR MICRO-CONTROLLER. 7.1 AREA AND PERFORMANCE RESULTS. 7.2 TMR 8051 MICRO-CONTROLLER RADIATION GROUND TEST RESULTS. 8. REDUCING TMR OVERHEADS: PART I. 8.1 DUPLICATION WITH COMPARISON COMBINED WITH TIME REDUNDANCY. 8.2 FAULT INJECTION IN THE VHDL DESCRIPTION. 8.3 AREA AND PERFORMANCE RESULTS. 9. REDUCING TMR OVERHEADS: PART II. 9.1 DWC-CED TECHNIQUE IN ARITHMETIC-BASED CIRCUITS. 9.1.1 Using CEDbased on hardware redundancy. 9.1.2 Using CED based on time redundancy. 9.1.3 Choosing the most appropriated CED block. 9.1.3.1 Multipliers. 9.1.3.2 Arithmetic and Logic Unit (ALU). 9.1.3.3 Digital FIR Filter. 9.1.4 Fault Coverage Results. 9.1.4 Area and Performance Results. 9.2 DESIGNING DWC-CED TECHNIQUE IN NON-ARITHMETIC-BASED CIRCUITS. 10. FINAL REMARKS. REFERENCES.
Series Title: Frontiers in electronic testing, 32.
Responsibility: by Fernanda Lima Kastensmidt, Luigi Carro and Ricardo Reis.
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