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From contamination to defects, faults, and yield loss : simulation and applications

Author: Jitendra B Khare; W Maly
Publisher: Boston : Kluwer Academic Publishers, ©1996.
Series: Frontiers in electronic testing.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the  Read more...

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Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Jitendra B Khare; W Maly
ISBN: 0792397142 9780792397144
OCLC Number: 34284663
Description: 150 pages : illustrations ; 24 cm.
Contents: Preface. 1: Introduction. 1.1. Trends in IC Manufacturing. 1.2. Yield Loss Mechanisms in ICs. 1.3. Functional Yield Estimation. 1.4. Research Goals. 1.5. Outline. 1.6. References. 2: Background. 2.1. Terminology. 2.2. Point Model. 2.3. Disk Model. 2.4. Experimental Investigation of the Disk Model. 2.5. Summary. 2.6. References. 3: Contamination-Defect-Fault (CDF) Simulation. 3.1. New Contamination Model. 3.2. Contamination-Defect-Fault (CDF) Simulation. 3.3. References. 4: CDF Mapper CODEF. 4.1. CODEF: An Overview. 4.2. Chip Data Base (CDB). 4.3. Process Models. 4.4. Circuit Extraction. 4.5. Netlist Comparison. 4.6. CODEF: Illustration. 4.7. Runtime and Memory Usage. 4.8. References. 5: CODEF Applications. 5.1. Yield Estimation. 5.2. Fault Modeling. 5.3. Failure Analysis. 5.4. References. 6: Possible Extensions. 6.1. CODEF Speed and Memory Considerations. 6.2. Addition of New Process Models. 6.3. Additional Contamination Properties. 6.4. Extraction of Bipolar Transistors. 6.5. Identification of Contamination Parameters. 6.6. References. 7: Conclusions. Appendix A: CMOS Process Flow. Index.
Series Title: Frontiers in electronic testing.
Responsibility: by Jitendra B. Khare, Wojciech Maly.
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