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Generating hardware assertion checkers : for hardware verification, emulation, post-fabrication debugging and on-line monitoring

Author: Marc Boulé; Zeljko Zilic
Publisher: Dordrecht : Springer, ©2008.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Boulé, Marc, 1974-
Generating hardware assertion checkers.
[S.l.] : Springer, ©2008
(OCoLC)227032778
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Marc Boulé; Zeljko Zilic
ISBN: 9781402085857 1402085850 9781402085864 1402085869 1281492302 9781281492302
OCLC Number: 242741899
Description: 1 online resource (xx, 279 pages)
Contents: Assertions and the Verification Landscape --
Basic Techniques Behind Assertion Checkers --
PSL and SVA Assertion Languages --
Automata for Assertion Checkers --
Construction of PSL Assertion Checkers --
Enhanced Features and Uses of PSL Checkers --
Evaluating and Verifying PSL Assertion Checkers --
Checkers for SystemVerilog Assertions --
Conclusions and Future Work.
Responsibility: Marc Boulé, Zeljko Zilic.

Abstract:

This book presents an "under-the-hood" view of generating assertion checkers. It gives a unique and consistent perspective on employing assertions in such areas as specification, verification,  Read more...

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