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Hierarchical Modeling for VLSI Circuit Testing

Author: Debashis Bhattacharya; John P Hayes
Publisher: Boston, MA : Springer US, 1990.
Series: Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing ;, 89.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Database:WorldCat
Summary:

To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel.

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Details

Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Debashis Bhattacharya; John P Hayes
ISBN: 9781461315278 1461315271
OCLC Number: 852791493
Description: 1 online resource (176 pages).
Contents: 1 Introduction --
1.1 Background --
1.2 Prior Work --
1.3 Outline --
2 Circuit and Fault Modeling --
2.1 Vector Sequence Notation --
2.2 Circuit and Fault Models --
2.3 Case Study: k-Regular Circuits --
3 Hierarchical Test Generation --
3.1 Vector Cubes --
3.2 Test Generation --
3.3 Implementation and Experimental Results --
4 Design for Testability --
4.1 Ad Hoc Techniques --
4.2 Level Separation (LS) Method --
4.3 Case Study: ALU --
5 Concluding Remarks --
5.1 Summary --
5.2 Future Directions --
Appendix A: Proofs of Theorems --
A.1 Proof of Theorem 3.2 --
A.2 Proof of Theorem 3.3 --
A.3 Proof of Theorem 4.1.
Series Title: Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing ;, 89.
Responsibility: by Debashis Bhattacharya, John P. Hayes.

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