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High speed signaling : jitter modeling, analysis, and budgeting

Author: Kyung Suk Oh; Xingchao Yuan
Publisher: Boston, MA : Pearson Education, ©2012.
Series: Prentice Hall modern semiconductor design series., Prentice Hall signal integrity library.
Edition/Format:   Print book : EnglishView all editions and formats
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Document Type: Book
All Authors / Contributors: Kyung Suk Oh; Xingchao Yuan
ISBN: 9780132826914 0132826917
OCLC Number: 727703042
Description: xv, 511 pages : illustrations ; 25 cm
Contents: Preface viiiChapter 1 Introduction 11.1 Signal Integrity Analysis Trends 41.2 Challenges of High-Speed Signal Integrity Design 81.3 Organization of This Book 9References 11Chapter 2 High-Speed Signaling Basics 132.1 I/O Signaling Basics and Components 132.2 Noise Sources 242.3 Jitter Basics and Decompositions 332.4 Summary 39References 39Part I Channel Modeling and Design 41Chapter 3 Channel Modeling and Design Methodology 433.1 Channel Design Methodology 443.2 Channel Modeling Methodology 493.3 Modeling with Electromagnetic Field Solvers 523.4 Backplane Channel Modeling Example 543.5 Summary 63References 64Chapter 4 Network Parameters 654.1 Generalized Network Parameters for Multi-Conductor Systems 664.2 Preparing an Accurate S-Parameter Time-Domain Model 774.3 Passivity Conditions 854.4 Causality Conditions 894.5 Summary 98References 101Chapter 5 Transmission Lines 1035.1 Transmission Line Theory 1045.2 Forward and Backward Crosstalk 1095.3 Time-Domain Simulation of Transmission Lines 1155.4 Modeling Transmission Line from Measurements 1215.5 On-Chip Wire Modeling 1365.6 Comparison of On-Chip, Package, and PCB Traces 1425.7 Summary 145References 145Part II Analyzing Link Performance 151Chapter 6 Channel Voltage and Timing Budget 1536.1 Timing Budget Equation and Components 1556.2 Fibre Channel Dual-Dirac Model 1566.3 Component-Level Timing Budget 1606.4 Pitfalls of Timing Budget Equation 1616.5 Voltage Budget Equations and Components 1646.6 Summary 165References 165Chapter 7 Manufacturing Variation Modeling 1677.1 Introduction to the Taguchi Method 1687.2 DDR DRAM Command/Address Channel Example 1797.3 Backplane Link Modeling Example 1867.4 Summary 1927.5 Appendix 193References 196Chapter 8 Link BER Modeling and Simulation 1978.1 Historical Background and Chapter Organization 1988.2 Statistical Link BER Modeling Framework 1998.3 Intersymbol Interference Modeling 2068.4 Transmitter and Receiver Jitter Modeling 2108.5 Periodic Jitter Modeling 2188.6 Summary 225References 226Chapter 9 Fast Time-Domain Channel Simulation Techniques 2299.1 Fast Time-Domain Simulation Flow Overview 2309.2 Fast System Simulation Techniques 2329.3 Simultaneous Switching Noise Example 2459.4 Comparison of Jitter Modeling Methods 2469.5 Peak Distortion Analysis 2489.6 Summary 253References 253Chapter 10 Clock Models in Link BER Analysis 25710.1 Independent and Common Clock Jitter Models 25810.2 Modeling Common Clocking Schemes 25910.3 CDR Circuitry Modeling 26810.4 Passive Channel JIF and Jitter Amplification 27310.5 Summary 277References 277Part III Supply Noise and Jitter 279Chapter 11 Overview of Power Integrity Engineering 28111.1 PDN Design Goals and Supply Budget 28211.2 Power Supply Budget Components 28311.3 Deriving a Power Supply Budget 28711.4 Supply Noise Analysis Methodology 29011.5 Steps in Power Supply Noise Analysis 29411.6 Summary 300References 301Chapter 12 SSN Modeling and Simulation 30312.1 SSN Modeling Challenges 30512.2 SI and PI Co-Simulation Methodology 31012.3 Signal Current Loop and Supply Noise 32112.4 Additional SSN Modeling Topics 32512.5 Case Study: DDR2 SSN Analysis for Consumer Applications 33012.6 Summary 336References 337Chapter 13 SSN Reduction Codes and Signaling 33913.1 Data Bus Inversion Code 34013.2 Pseudo Differential Signaling Based on 4b6b Code 34613.3 Summary 357References 357Chapter 14 Supply Noise and Jitter Characterization 35914.1 Importance of Supply Noise Induced Jitter 36014.2 Overview of PSIJ Modeling Methodology 36114.3 Noise and Jitter Simulation Methodology 36414.4 Case Study 37214.5 Summary 376References 377Chapter 15 Substrate Noise Induced Jitter 37915.1 Introduction 38015.2 Modeling Techniques 38215.3 Measurement Techniques 39115.4 Case Study 39315.5 Summary 400References 400Part IV Advanced Topics 403Chapter 16 On-Chip Link Measurement Techniques 40516.1 Shmoo and BER Eye Diagram Measurements 40716.2 Capturing Signal Waveforms 40816.3 Link Performance Measurement and Correlation 41116.4 On-Chip Supply Noise Measurement Techniques 41216.5 Advanced Power Integrity Measurements 41816.6 Summary 422References 423Chapter 17 Signal Conditioning 42517.1 Single-Bit Response 42617.2 Equalization Techniques 42717.3 Equalization Adaptation Algorithms 43317.4 CDR and Equalization Adaptation Interaction 44217.5 ADC-Based Receive Equalization 44517.6 Future of High-Speed Wireline Equalization 44817.7 Summary 449References 450Chapter 18 Applications 45518.1 XDR: High-Performance Differential Memory System 45618.2 Mobile XDR: Low Power Differential Memory System 46518.3 Main Memory Systems beyond DDR3 47618.4 Future Signaling Systems 486References 491Index 495
Series Title: Prentice Hall modern semiconductor design series., Prentice Hall signal integrity library.
Responsibility: edited by Kyung Suk (Dan) Oh, Xingchao (Chuck) Yuan.

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