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Hot-carrier reliability of MOS VLSI circuits

Author: Yusuf Leblebici; Sung-Mo Kang
Publisher: Boston : Kluwer Academic, ©1993.
Series: Kluwer international series in engineering and computer science, SECS 227.; Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is  Read more...

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Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Yusuf Leblebici; Sung-Mo Kang
ISBN: 079239352X 9780792393528
OCLC Number: 27937993
Description: xvi, 212 pages : illustrations ; 25 cm.
Contents: 1. Introduction --
1.1. The Concept of IC Reliability --
1.2. Design-for-Reliability --
1.3. VLSI Reliability Problems --
1.4. Gradual Degradation versus Catastrophic Failures --
1.5. Hot-Carrier Effects --
2. Oxide Degradation Mechanisms in MOS Transistors --
2.2. MOS Transistor : A Qualitative View --
2.3. The Nature of Gate Oxide Damage in MOSFETs --
2.4. Injection of Hot Carriers into Gate Oxide --
2.5. Oxide Traps and Charge Trapping --
2.6. Interface Trap Generation --
2.7. Bias Dependence of Degradation Mechanisms --
2.8. Degradation under Dynamic Operating Conditions --
2.9. Effects of Hot-Carrier Damage on Device Characteristics --
2.10. Hot-Carrier Induced Degradation of pMOS Transistors --
3. Modeling of Degradation Mechanisms --
3.2. Quasi-Elastic Scattering Current Model --
3.3. Charge (Electron) Trapping Model --
3.4. Impact Ionization Current Model --
3.5. Interface Trap Generation Model --
3.6. Trap Generation under Dynamic Operating Conditions --
4. Modeling of Damaged MOSFETs --
4.2. Representation of Hot-Carrier Induced Oxide Damage --
4.3. Two-Dimensional Modeling of Damaged MOSFETs --
4.4. Empirical One-Dimensional Modeling --
4.5. An Analytical Damaged MOSFET Model --
4.6. Consideration of Channel Velocity Limitations --
4.7. Pseudo Two-Dimensional Modeling of Damaged MOSFETs --
4.8. Table-Based Modeling Approaches --
5. Transistor-Level Simulation for Circuit Reliability --
5.2. Review of Circuit Reliability Simulation Tools --
5.3. Circuit Reliability Simulation Using iSMILE : A Case Study --
5.4. Circuit Simulation Examples --
5.5. Evaluation of the Simulation Algorithm --
5.6. Identification of Critical Devices --
6. Fast Timing Simulation for Circuit Reliability --
6.2. ILLIADS-R : A Fast Timing and Reliability Simulator --
6.3. Fast Dynamic Reliability Simulation --
6.4. Circuit Simulation Examples with ILLIADS-R --
6.5. iDSIM2 : Hierarchical Circuit Reliability Simulation --
7. Macromodeling of Hot-Carrier Induced Degradation in MOS Circuits --
7.2. Macromodel Development : Starting Assumptions --
7.3. Degradation Macromodel for CMOS Inverters --
7.4. Degradation Macromodel for nMOS Pass Gates --
7.5. Application of the Macromodel to Inverter Chain Circuits --
7.6. Application of the Macromodel to CMOS Logic Circuits --
8. Circuit Design for Reliability --
8.2. Device-Level Measures --
8.3. Circuit-Level Measures --
8.4. Rule-Based Diagnosis of Circuit Reliability.
Series Title: Kluwer international series in engineering and computer science, SECS 227.; Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing.
Responsibility: by Yusuf Leblebici, Sung-Mo (Steve) Kang.
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