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Integrated circuit design : power and timing modeling, optimization, and simulation : 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 : proceedings

Author: Dimitrios Soudris; P Pirsch; Erich Barke
Publisher: Berlin ; New York : Springer, 2000.
Series: Lecture notes in computer science, 1918.
Edition/Format:   Print book : Conference publication : EnglishView all editions and formats
Database:WorldCat
Summary:

The papers in this book cover topics such as RTL power modeling, power esti mation and optimization, system-level design, transistor level design, asynchronous circuit design, power efficient  Read more...

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Genre/Form: Conference papers and proceedings
Congresses
Material Type: Conference publication, Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Dimitrios Soudris; P Pirsch; Erich Barke
ISBN: 3540410686 9783540410683
OCLC Number: 44883848
Description: xii, 338 pages : illustrations ; 23 cm.
Contents: Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action / R. van Leuken, R. Nouta and A. de Graf --
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques / M. Anton, M. Chinosi and D. Sirtori / [et al.] --
Power Models for Semi-autonomous RTL Macros / A. Bogliolo, E. Macii and V. Mihailovici / [et al.] --
Power Macro-Modelling for Firm-Macro / G. Jochens, L. Kruse and E. Schmidt / [et al.] --
RTL Estimation of Steering Logic Power / C. Anton, P. Civera and I. Colonescu / [et al.] --
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers / N. D. Zervas, S. Theoharis and A. P. Kakaroudas / [et al.] --
Framework for High-Level Power Estimation of Signal Processing Architectures / A. Freimann --
Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses / C. Kretzschmar, R. Siegmund and D. Muller --
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions / G. Theodoridis, S. Theoharis and N. D. Zervas / [et al.] --
A Holistic Approach to System Level Energy Optimization / M. J. Irwin, M. Kandemir and N. Vijaykrishnan / [et al.] --
Early Power Estimation for System-on-Chip Designs / M. Lajolo, L. Lavagno and M. Sonza Reorda / [et al.] --
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures / R. Hartenstein, Th. Hoffmann and U. Nageldinger --
Internal Power Dissipation Modelling and Minimization for Submicronic CMOS Design / P. Maurine, M. Rezzoug and D. Auvergne --
Impact of Voltage Scaling on Glitch Power Consumption / H. Eriksson and P. Larsson-Edefors --
Degradation Delay Model Extension to CMOS Gates / J. Juan-Chico, M. J. Bellido and P. Ruiz-de-Clavijo / [et al.] --
Second Generation Delay Model for Submicron CMOS Process / M. Rezzoug, P. Maurine and D. Auvergne --
Semi-modular Latch Chains for Asynchronous Circuit Design / N. Starodoubtsev, A. Bystrov and A. Yakovlev --
Asynchronous First-in First-out Queues / F. Pessolano and J. W. L. Kessels --
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance / A. P. Kakaroudas, K. Papadomanolakis and V. Kokkinos / [et al.] --
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder / P. Corsonello, S. Perri and G. Cocorullo --
Low Power Design Techniques for Contactless Chipcards / H. Sedlak --
Dynamic Memory Design for Low Data-Retention Power / J. Kim and M. C. Papaefthymiou --
Double-Latch Clocking Scheme for Low-Power I.P. Cores / C. Arm, J.-M. Masgonty and C. Piguet --
Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip / S. Dutta --
Cost-Efficient C-Level Design of an MPEG-4 Video Decoder / K. Denolf, P. Vos and J. Bormans / [et al.] --
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications / D. Soudris, A. Argyriou and M. Dasygenis / [et al.] --
Design of Reversible Logic Circuits by Means of Control Gates / A. De Vos, B. Desoete and A. Adamski / [et al.] --
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates / M. Alioto and G. Palumbo --
An Adiabatic Multiplier / C. Saas, A. Schlaffer and J. A. Nossek --
Logarithmic Number System for Low-Power Arithmetic / V. Paliouras and T. Stouraitis --
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits / R. Jimenez, A. J. Acosta and E. J. Peralias / [et al.] --
PARCOURS --
Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits / A. Hermann, E. Barke and M. Silvant / [et al.] --
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits / A. J. Acosta, R. Jimenez and J. Juan / [et al.] --
Computer Aided Generation of Analytic Models for Nonlinear Function Blocks / T. Wichmann and M. Thole.
Series Title: Lecture notes in computer science, 1918.
Responsibility: Dimitrios Soudris, Peter Pirsch, Erich Barke (eds.).
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