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Integrating Functional and Temporal Domains in Logic Design : the False Path Problem and Its Implications

Author: Patrick C McGeer; Robert K Brayton
Publisher: Boston, MA : Springer US, 1991.
Series: Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing, 139.
Edition/Format:   eBook : Document : EnglishView all editions and formats
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After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by  Read more...

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Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Patrick C McGeer; Robert K Brayton
ISBN: 9781461539605 1461539609
OCLC Number: 851782299
Description: 1 online resource (xxiii, 212 pages).
Contents: 1 Introduction.- 1.1 Timing Analysis of Circuits.- 1.1.1 Delay Models.- 1.1.2 Graph Theory Formulation.- 1.2 The General False Path Problem.- 1.2.1 Explicit Recording of False Paths.- 1.2.2 Case Analysis.- 1.2.3 Directionality Tags on Pass Transistors.- 1.2.4 Automated Solutions.- 1.3 A Note on Notation.- 1.3.1 On "Implications".- 1.3.2 A Final Word on Notation.- 1.4 Logic Notation.- 1.4.1 Cubes.- 1.4.2 Cofactors.- 1.4.3 A Family of Operators.- 1.5 Outline.- 2 The False Path Problem.- 2.1 Introduction.- 2.2 Dynamic Timing Analysis.- 2.3 Viable Paths.- 2.4 Symmetric Networks and Monotonicity.- 2.5 Viability Under Network Transformations.- 2.6 The Viability Function.- 2.7 Summary.- 3 False Path Detection Algorithms.- 3.1 Generic False Path Detection Algorithm.- 3.1.1 Depth-First Search.- 3.1.2 Best-First Search.- 3.1.3 Generic Procedure.- 3.1.4 Modifying the Generic Procedure to find Every Long True Path.- 3.1.5 Varying Input Times, Output Times, and Slacks.- 3.1.6 Separate Rise and Fall Delays.- 3.1.7 Don't-Care Conditions.- 3.2 Viability Analysis Procedure.- 3.2.1 Naive Depth-First Search Procedure.- 3.2.2 Dynamic Programming Procedure.- 3.3 Dynamic Programming Algorithm Example.- 3.4 Finding all the Longest Viable Paths.- 3.5 Recent Work.- 4 System Considerations and Approximations.- 4.1 Approximation Theory and Practice.- 4.2 "Weak" Viability.- 4.3 The Brand-Iyengar Procedure.- 4.4 The Du-Yen-Ghanta Criteria.- 4.5 The Chen-Du Criterion.- 4.6 More Macroexpansion Transformations.- 4.7 Biased Satisfiability Tests.- 4.8 Axes of Approximation.- 4.9 The Lllama Timing Environment.- 4.10 Experimental Results.- 5 Hazard Prevention in Combinational Circuits.- 5.1 Introduction.- 5.2 Hazards.- 5.3 The Boolean n-Space.- 5.4 The SDC Set and Restricted Cubes.- 5.5 Ordering The Inputs.- 6 Timing Analysis in Hazard-Free Networks.- 6.1 Introduction.- 6.2 Robustness of Dynamic Sensitization.- 6.3 The Dynamic Sensitization Function.- 6.4 Algorithms.- 6.5 Conclusion.- A Complexity Results.- A.1 An Introduction to Polynomial Reducibility.- B A Family of Operators.- C Fast Procedures for Computing Dataflow Sets.- C.1 Introduction.- C.2 Terminology.- C.3 The New Approach.- C.4 Computations.- C.4.1 Basic Algorithms.- C.4.2 Transitivity.- C.4.4 Evaluation Algorithms.- C.5 Correctness.- C.6 Complexity Analysis.- C.7 Efficiency.- C.8 Sparse Matrix Implementation.- C.9 An Improvement.- C.10 Results.- C.11 Extensions.- C.11.1 Extending Arbitrary Cubes.- C.11.2 The Fanout Care Set and the Test Function.- D Precharged, Unate Circuits.
Series Title: Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing, 139.
Responsibility: by Patrick C. McGeer, Robert K. Brayton.

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Linked Data


Primary Entity

<http://www.worldcat.org/oclc/851782299> # Integrating Functional and Temporal Domains in Logic Design : the False Path Problem and Its Implications
    a schema:Book, schema:MediaObject, schema:CreativeWork ;
   library:oclcnum "851782299" ;
   library:placeOfPublication <http://experiment.worldcat.org/entity/work/data/25175317#Place/boston_ma> ; # Boston, MA
   library:placeOfPublication <http://id.loc.gov/vocabulary/countries/mau> ;
   schema:about <http://dewey.info/class/620.00420285/e23/> ;
   schema:about <http://id.worldcat.org/fast/872701> ; # Computer-aided design
   schema:about <http://id.worldcat.org/fast/872451> ; # Computer science
   schema:about <http://id.worldcat.org/fast/872078> ; # Computer engineering
   schema:bookFormat schema:EBook ;
   schema:contributor <http://viaf.org/viaf/51841890> ; # Robert K. Brayton
   schema:creator <http://viaf.org/viaf/111945306> ; # Patrick C. McGeer
   schema:datePublished "1991" ;
   schema:exampleOfWork <http://worldcat.org/entity/work/id/25175317> ;
   schema:genre "Electronic books"@en ;
   schema:inLanguage "en" ;
   schema:isPartOf <http://experiment.worldcat.org/entity/work/data/25175317#Series/springer_international_series_in_engineering_and_computer_science_vlsi_computer_architecture_and_digital_signal_processing> ; # Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing ;
   schema:isPartOf <http://worldcat.org/issn/0893-3405> ; # The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing,
   schema:isSimilarTo <http://worldcat.org/entity/work/data/25175317#CreativeWork/> ;
   schema:name "Integrating Functional and Temporal Domains in Logic Design : the False Path Problem and Its Implications"@en ;
   schema:productID "851782299" ;
   schema:publication <http://www.worldcat.org/title/-/oclc/851782299#PublicationEvent/boston_ma_springer_us_1991> ;
   schema:publisher <http://experiment.worldcat.org/entity/work/data/25175317#Agent/springer_us> ; # Springer US
   schema:url <http://public.eblib.com/choice/publicfullrecord.aspx?p=3081618> ;
   schema:url <http://link.springer.com/10.1007/978-1-4615-3960-5> ;
   schema:url <http://dx.doi.org/10.1007/978-1-4615-3960-5> ;
   schema:workExample <http://dx.doi.org/10.1007/978-1-4615-3960-5> ;
   schema:workExample <http://worldcat.org/isbn/9781461539605> ;
   wdrs:describedby <http://www.worldcat.org/title/-/oclc/851782299> ;
    .


Related Entities

<http://experiment.worldcat.org/entity/work/data/25175317#Series/springer_international_series_in_engineering_and_computer_science_vlsi_computer_architecture_and_digital_signal_processing> # Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing ;
    a bgn:PublicationSeries ;
   schema:hasPart <http://www.worldcat.org/oclc/851782299> ; # Integrating Functional and Temporal Domains in Logic Design : the False Path Problem and Its Implications
   schema:name "Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing ;" ;
    .

<http://id.worldcat.org/fast/872078> # Computer engineering
    a schema:Intangible ;
   schema:name "Computer engineering"@en ;
    .

<http://id.worldcat.org/fast/872451> # Computer science
    a schema:Intangible ;
   schema:name "Computer science"@en ;
    .

<http://id.worldcat.org/fast/872701> # Computer-aided design
    a schema:Intangible ;
   schema:name "Computer-aided design"@en ;
    .

<http://link.springer.com/10.1007/978-1-4615-3960-5>
   rdfs:comment "from Springer" ;
   rdfs:comment "(Unlimited Concurrent Users)" ;
    .

<http://viaf.org/viaf/111945306> # Patrick C. McGeer
    a schema:Person ;
   schema:familyName "McGeer" ;
   schema:givenName "Patrick C." ;
   schema:name "Patrick C. McGeer" ;
    .

<http://viaf.org/viaf/51841890> # Robert K. Brayton
    a schema:Person ;
   schema:familyName "Brayton" ;
   schema:givenName "Robert K." ;
   schema:name "Robert K. Brayton" ;
    .

<http://worldcat.org/entity/work/data/25175317#CreativeWork/>
    a schema:CreativeWork ;
   schema:description "Print version:" ;
   schema:isSimilarTo <http://www.worldcat.org/oclc/851782299> ; # Integrating Functional and Temporal Domains in Logic Design : the False Path Problem and Its Implications
    .

<http://worldcat.org/isbn/9781461539605>
    a schema:ProductModel ;
   schema:isbn "1461539609" ;
   schema:isbn "9781461539605" ;
    .

<http://worldcat.org/issn/0893-3405> # The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing,
    a bgn:PublicationSeries ;
   schema:hasPart <http://www.worldcat.org/oclc/851782299> ; # Integrating Functional and Temporal Domains in Logic Design : the False Path Problem and Its Implications
   schema:issn "0893-3405" ;
   schema:name "The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing," ;
    .

<http://www.worldcat.org/title/-/oclc/851782299>
    a genont:InformationResource, genont:ContentTypeGenericResource ;
   schema:about <http://www.worldcat.org/oclc/851782299> ; # Integrating Functional and Temporal Domains in Logic Design : the False Path Problem and Its Implications
   schema:dateModified "2017-12-24" ;
   void:inDataset <http://purl.oclc.org/dataset/WorldCat> ;
    .


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