RT Book, Whole DB /z-wcorg/ DS http://worldcat.org ID 40534543 LA English T1 Logical effort : designing fast CMOS circuits A1 Sutherland, Ivan Edward,, Sproull, Robert F., Harris, David, PB Morgan Kaufmann Publishers PP San Francisco, Calif. YR 1999 SN 1558605576 9781558605572 AB Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high-speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes. The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts - so you can apply it immediately. Later chapters explore the theory behind the method and detail its specialized applications.