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Logical effort : designing fast CMOS circuits

Autor Ivan Edward Sutherland; Robert F Sproull; David Harris
Vydavatel: San Francisco, Calif. : Morgan Kaufmann Publishers, ©1999.
Vydání/formát:   Kniha : EnglishZobrazit všechny vydání a formáty
Databáze:WorldCat
Shrnutí:
Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high-speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.
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Detaily

Doplňující formát: Online version:
Sutherland, Ivan Edward, 1938-
Logical effort.
San Francisco, Calif. : Morgan Kaufmann Publishers, ©1999
(OCoLC)607221365
Typ materiálu: Internetový zdroj
Typ dokumentu: Book, Internet Resource
Všichni autoři/tvůrci: Ivan Edward Sutherland; Robert F Sproull; David Harris
ISBN: 1558605576 9781558605572
OCLC číslo: 40534543
Popis: xv, 239 pages : illustrations ; 24 cm
Obsahy: 1. The Method of Logical Effort --
2. Design Examples --
3. Deriving the Method of Logical Effort --
4. Calculating the Logical Effort of Gates --
5. Calibrating the Model --
6. Asymmetric Logic Gates --
7. Unequal Rising and Falling Delays --
8. Circuit Families --
9. Forks of Amplifiers --
10. Branches and Interconnect --
11. Wide Structures --
12. Concluisons --
App. A. Cast of Characters --
App. B. Reference Process Parameters --
App. C. Solutions to Selected Exercises.
Odpovědnost: Ivan Sutherland, Robert Sproull, David Harris.
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Anotace:

Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high-speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.

The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts - so you can apply it immediately. Later chapters explore the theory behind the method and detail its specialized applications.

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<http://www.worldcat.org/oclc/40534543>
library:oclcnum"40534543"
library:placeOfPublication
library:placeOfPublication
rdf:typeschema:Book
rdf:typeschema:MediaObject
schema:about
<http://id.loc.gov/authorities/subjects/sh2008107701>
rdf:typeschema:Intangible
schema:name"Metal oxide semiconductors, Complementary--Design and construction."@en
schema:about
<http://id.worldcat.org/fast/889913>
rdf:typeschema:Intangible
schema:name"Metal oxide semiconductors, Complementary--Design and construction."@en
schema:about
schema:about
schema:about
schema:about
schema:about
schema:about
schema:about
schema:contributor
schema:contributor
schema:copyrightYear"1999"
schema:creator
schema:datePublished"1999"
schema:description"The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts - so you can apply it immediately. Later chapters explore the theory behind the method and detail its specialized applications."@en
schema:description"Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high-speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes."@en
schema:exampleOfWork<http://worldcat.org/entity/work/id/312227148>
schema:inLanguage"en"
schema:name"Logical effort : designing fast CMOS circuits"@en
schema:publication
schema:publisher
schema:workExample
umbel:isLike<http://bnb.data.bl.uk/id/resource/GB9928590>
wdrs:describedby

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