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Logical effort : designing fast CMOS circuits

Autor: Ivan Edward Sutherland; Robert F Sproull; David Harris
Editorial: San Francisco, Calif. : Morgan Kaufmann Publishers, ©1999.
Edición/Formato:   Print book : Inglés (eng)Ver todas las ediciones y todos los formatos
Base de datos:WorldCat
Resumen:
Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high-speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.
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Formato físico adicional: Online version:
Sutherland, Ivan Edward, 1938-
Logical effort.
San Francisco, Calif. : Morgan Kaufmann Publishers, ©1999
(OCoLC)607221365
Tipo de material: Recurso en Internet
Tipo de documento: Libro/Texto, Recurso en Internet
Todos autores / colaboradores: Ivan Edward Sutherland; Robert F Sproull; David Harris
ISBN: 1558605576 9781558605572
Número OCLC: 40534543
Descripción: xv, 239 pages : illustrations ; 24 cm
Contenido: 1. The Method of Logical Effort --
2. Design Examples --
3. Deriving the Method of Logical Effort --
4. Calculating the Logical Effort of Gates --
5. Calibrating the Model --
6. Asymmetric Logic Gates --
7. Unequal Rising and Falling Delays --
8. Circuit Families --
9. Forks of Amplifiers --
10. Branches and Interconnect --
11. Wide Structures --
12. Concluisons --
App. A. Cast of Characters --
App. B. Reference Process Parameters --
App. C. Solutions to Selected Exercises.
Responsabilidad: Ivan Sutherland, Robert Sproull, David Harris.
Más información:

Resumen:

Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high-speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.

The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts - so you can apply it immediately. Later chapters explore the theory behind the method and detail its specialized applications.

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