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Logical effort : designing fast CMOS circuits

著者: Ivan Edward Sutherland; Robert F Sproull; David Harris
出版: San Francisco, Calif. : Morgan Kaufmann Publishers, ©1999.
エディション/フォーマット:   book_printbook : Englishすべてのエディションとフォーマットを見る
データベース:WorldCat
概要:
Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high-speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.
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その他のフォーマット: Online version:
Sutherland, Ivan Edward, 1938-
Logical effort.
San Francisco, Calif. : Morgan Kaufmann Publishers, ©1999
(OCoLC)607221365
資料の種類: インターネット資料
ドキュメントの種類: 図書, インターネットリソース
すべての著者/寄与者: Ivan Edward Sutherland; Robert F Sproull; David Harris
ISBN: 1558605576 9781558605572
OCLC No.: 40534543
物理形態: xv, 239 pages : illustrations ; 24 cm
コンテンツ: 1. The Method of Logical Effort --
2. Design Examples --
3. Deriving the Method of Logical Effort --
4. Calculating the Logical Effort of Gates --
5. Calibrating the Model --
6. Asymmetric Logic Gates --
7. Unequal Rising and Falling Delays --
8. Circuit Families --
9. Forks of Amplifiers --
10. Branches and Interconnect --
11. Wide Structures --
12. Concluisons --
App. A. Cast of Characters --
App. B. Reference Process Parameters --
App. C. Solutions to Selected Exercises.
責任者: Ivan Sutherland, Robert Sproull, David Harris.
その他の情報:

概要:

Includes chapters that explore the theory and finer points of logical effort method and detail its specialized applications. This book offers coverage of specialized areas of application for logical  続きを読む

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