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Logical effort : designing fast CMOS circuits

Auteur: Ivan Edward Sutherland; Robert F Sproull; David Harris
Uitgever: San Francisco, Calif. : Morgan Kaufmann Publishers, ©1999.
Editie/Formaat:   Print book : EngelsAlle edities en materiaalsoorten bekijken.
Database:WorldCat
Samenvatting:
Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high-speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.
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Details

Aanvullende fysieke materiaalsoort: Online version:
Sutherland, Ivan Edward, 1938-
Logical effort.
San Francisco, Calif. : Morgan Kaufmann Publishers, ©1999
(OCoLC)607221365
Genre: Internetbron
Soort document: Boek, Internetbron
Alle auteurs / medewerkers: Ivan Edward Sutherland; Robert F Sproull; David Harris
ISBN: 1558605576 9781558605572
OCLC-nummer: 40534543
Beschrijving: xv, 239 pages : illustrations ; 24 cm
Inhoud: 1. The Method of Logical Effort --
2. Design Examples --
3. Deriving the Method of Logical Effort --
4. Calculating the Logical Effort of Gates --
5. Calibrating the Model --
6. Asymmetric Logic Gates --
7. Unequal Rising and Falling Delays --
8. Circuit Families --
9. Forks of Amplifiers --
10. Branches and Interconnect --
11. Wide Structures --
12. Concluisons --
App. A. Cast of Characters --
App. B. Reference Process Parameters --
App. C. Solutions to Selected Exercises.
Verantwoordelijkheid: Ivan Sutherland, Robert Sproull, David Harris.
Meer informatie:

Fragment:

Includes chapters that explore the theory and finer points of logical effort method and detail its specialized applications. This book offers coverage of specialized areas of application for logical  Meer lezen...

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