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Logical effort designing fast CMOS circuits

Author: Ivan Sutherland; David Harris; Bob Sproull
Publisher: San Francisco, Calif. Morgan Kaufmann [20]08.
Edition/Format:   Print book : English : [Nachdr.View all editions and formats
Database:WorldCat
Summary:

Includes chapters that explore the theory and finer points of logical effort method and detail its specialized applications. This book offers coverage of specialized areas of application for logical  Read more...

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Document Type: Book
All Authors / Contributors: Ivan Sutherland; David Harris; Bob Sproull
ISBN: 9781558605572 1558605576
OCLC Number: 669792617
Description: XV, 239 S. graph. Darst.
Contents: 1 The Method of Logical Effort 2 Design Examples 3 Deriving the Method of Logical Effort 4 Calculating the Logical Effort of Gates 5 Calibrating the Model 6 Asymmetric Logic Gates 7 Unequal Rising and Falling Delays 8 Circuit Families 9 Forks of Amplifiers 10 Branches and Interconnect 11 Wide Structures 12 Conclusions A Cast of Characters B Reference process parameters C Logical Effort Tools D Solutions
Responsibility: Ivan Sutherland ; Bob Sproull ; David Harris.

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