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Low-Power Deep Sub-Micron CMOS Logic : Sub-threshold Current Reduction

Author: P R Meer; A Staveren; A H M Roermund
Publisher: Boston, MA : Springer US, 2004.
Series: Kluwer international series in engineering and computer science., Analog circuits and signal processing ;, 841.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
The strong interaction between the demand for increasing chip functionality and data-processing speeds, and technological trends in the integrated circuit industry, like e.g. shrinking device geometry, growing chip area and increased transistor switching speeds, cause a huge increase in power dissipation for deep sub-micron digital CMOS circuits. Low-Power Deep Sub-micron CMOS Logic, Sub-threshold Current Reduction  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: P R Meer; A Staveren; A H M Roermund
ISBN: 9781402028496 1402028490
OCLC Number: 853269883
Description: 1 online resource (xiv, 154 pages with CD-ROM.).
Contents: Index of Symbols --
1. Introduction --
2. Power Versus Energy --
3. Power Dissipation in Digital CMOS Circuits --
4. Reduction of Functional Power Dissipation --
5. Reduction of Parasitical Power Dissipation --
6. Weak-inversion Current Reduction --
7. Effectiveness of Weak-inversion Current Reductions --
8. Triple-S Circuit Designs --
9. Conclusions --
10. Summary --
References --
Index.
Series Title: Kluwer international series in engineering and computer science., Analog circuits and signal processing ;, 841.
Responsibility: by P.R. Meer, A. Staveren, A.H.M. Roermund.

Abstract:

1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to  Read more...

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