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Microwave devices, circuits and subsystems for communications engineering

Author: Ian Glover; S R Pennock; Peter Shepherd
Publisher: Chichester, England ; Hoboken, NJ : John Wiley & Sons, ©2005.
Edition/Format:   eBook : Document : EnglishView all editions and formats
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Microwave devices, circuits and subsystems for communications engineering.
Chichester, England ; Hoboken, NJ : John Wiley & Sons, ©2005
(OCoLC)59135306
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Ian Glover; S R Pennock; Peter Shepherd
ISBN: 047189964X 9780471899648 9781601193797 1601193793 0470012749 9780470012741 0470012757 9780470012758
OCLC Number: 192143775
Reproduction Notes: Electronic reproduction. [S.l.] : HathiTrust Digital Library, 2010. MiAaHDL
Description: 1 online resource (xviii, 531 pages) : illustrations : digital, HTML and PDF files
Details: Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002.
Contents: Cover Table of Contents List of Acronyms and Symbols Preface 1 Introduction 1.1 MOTIVATION 1.2 SUMMARY OF BOOK 1.3 BOOK ORGANIZATION REFERENCES 2 Frequency Synthesizer for Wireless Applications 2.1 DEFINITION AND CHARACTERISTICS 2.2 PHASE NOISE AND TIMING JITTER 2.3 IMPLEMENTATION OF FREQUENCY SYNTHESIZER 2.4 FREQUENCY SYNTHESIZER FOR WIRELESS TRANSCEIVERS 2.5 OTHER APPLICATIONS OF PLL AND FREQUENCY SYNTHESIZER REFERENCES 3 PLL Frequency Synthesizer 3.1 PLL FREQUENCY SYNTHESIZER BASICS 3.2 FAST-LOCKING TECHNIQUES 3.3 DISCRETE-TIME ANALYSIS AND NONLINEAR MODELING 3.4 DESIGN EXAMPLE: 2.4GHZ INTEGER-N PLL FOR BLUETOOTH REFERENCES 4 EA Fractional-N PLL Synthesizer 4.1 EA FRACTIONAL-N FREQUENCY SYNTHESIZER 4.2 A COMPARATIVE STUDY OF DIGITAL EA MODULATORS 4.3 OTHER APPLICATIONS OF EA-PLL 4.4 MODELING AND SIMULATION OF EA-PLL 4.5 DESIGN EXAMPLE: 900MHz EA-PLL FOR GSM REFERENCES 5 Enhanced Phase Switching Prescaler 5.1 PRESCALER ARCHITECTURE 5.2 ENHANCED PHASE-SWITCHING PRESCALER 5.3 CIRCUIT DESIGN AND SIMULATION RESULTS 5.4 DELAY BUDGET IN THE SWITCHING CONTROL LOOP 5.5 SPURS DUE TO NONIDEAL 45 PHASE SPACING REFERENCES 6 Loop Filter With Capacitance Multiplier 6.1 LOOP FILTER ARCHITECTURE 6.2 LOOP FILTER AND CHARGE-PUMP NOISE MAPPING 6.3 LOOP FILTER WITH CAPACITANCE MULTIPLIER REFERENCES 7 Other Building Blocks of PLL 7.1 VCO 7.2 PHASE-FREQUENCY DETECTOR 7.3 CHARGE-PUMP 7.4 PROGRAMMABLE DIVIDER 7.5 DIGITAL EA MODULATOR 7.6 CHIP LAYOUT REFERENCES 8 Prototype Measurement Results 8.1 PRESCALER MEASUREMENT 8.2 LOOP FILTER MEASUREMENT 8.3 PLL MEASUREMENT REFERENCES 9 Conclusions Appendix.
Responsibility: edited by I.A. Glover, S.R. Pennock and P.R. Shepherd.
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