omitir hasta el contenido
Nano-CMOS design for manufacturability : robust circuit and physical design for sub-65 nm technology nodes Ver este material de antemano
CerrarVer este material de antemano
Chequeando…

Nano-CMOS design for manufacturability : robust circuit and physical design for sub-65 nm technology nodes

Autor: Ban P Wong; et al
Editorial: Hoboken, NJ : Wiley, ©2009.
Edición/Formato:   Libro-e : Documento : Inglés (eng)Ver todas las ediciones y todos los formatos
Base de datos:WorldCat
Resumen:
"Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also  Leer más
Calificación:

basada en 1 calificación/es 1 con una reseña

Temas
Más materiales como éste

 

Encontrar un ejemplar en línea

Enlaces a este material

Encontrar un ejemplar en la biblioteca

&AllPage.SpinnerRetrieving; Encontrando bibliotecas que tienen este material…

Detalles

Género/Forma: Electronic books
Formato físico adicional: Print version:
Nano-CMOS design for manufacturability.
Hoboken, NJ : Wiley, c2009
(DLC) 2008007589
(OCoLC)212375857
Tipo de material: Documento, Recurso en Internet
Tipo de documento: Recurso en Internet, Archivo de computadora
Todos autores / colaboradores: Ban P Wong; et al
ISBN: 9781615831753 1615831754 9780470382820 0470382821 9780470382813 0470382813
Número OCLC: 491221873
Descripción: 1 online resource (xv, 385 p.) : ill.
Contenido: 1. Introduction.1.1 DFM - Value proposition.1.2 Deficiencies in Boolean-based Design Rules in the sub-wavelength regime [6].1.3 Impact of Variability on Yield and Performance.1.4 The industry challenge - disappearing process window.1.5 Mobility enhancement techniques - a new source of variability induced by design process interaction.1.6 Design dependency of chip surface topology.1.7 Newly exacerbated narrow width effect in nano-CMOS nodes.1.8 Well proximity effect.1.9 Scaling beyond 65nm drives the need for model based DFM solutions.1.10 Summary.PART 1: NEWLY EXACERBATED EFFECTS.2. Lithography related Aspects of DFM.2.1 Economic motivations for DFM.2.2 Lithographic tools and techniques for advanced technology nodes.2.3 Lithography limited yield.2.4 Lithography driven DFM Solutions.3. Interaction of layout with transistor performance and stress engineering techniques.3.1 Introduction.3.2 Impact of stress on transistor performance.3.3 Stress propagation.3.4 Stress sources.3.5 Introducing stress into transistors.PART 2: DESIGN SOLUTIONS.4. Signal and Power Integrity.4.1 Introduction.4.2 Interconnect Resistance, Capacitance and Inductance.4.3 Inductance Effects on Interconnect.5. Analog and Mixed Signal Circuit Design for Yield and Manufacturability.5.1 Introduction.5.2 Guidelines.5.3 Device Selection.5.4 Device Size Heart Beat.5.5 Device Matching.5.6 Design Guidelines.5.7 Layout Guidelines.5.8 Test.6. Design for Variability, Performance and Yield.6.1 Introduction.6.2 Impact of variations (introduced by both process and circuit operation) on the design.6.3 Some Parametric Fluctuations with new implications for design .6.4 Process Variations in Interconnects.6.5 Impact of Deep Sub-Micron Integration in SRAMs.6.6 Impact of Layout Styles on Manufacturability, Yield and Scalability.6.7 Design for variations.6.8 Summary.PART 3: THE ROAD TO DFM.7. Nano-CMOS design tools: Beyond model-based analysis and correction.7.1 Introduction.7.2 Electrical Design for Manufacturability (DFM).7.3 Criticality Aware DFM.7.4 On Guardbands, Statistics, and Gaps.7.5 Opportunistic Mindsets.7.6 Futures at o 45nm .7.7 Summary.7.8 References.
Responsabilidad: Ban Wong ... [et al.].
Más información:

Resumen:

"Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also tackle complex issues in the design process to overcome the difficulties, including the use of a functional first silicon to support a predictable product ramp. Moreover, they introduce several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions."--BOOK JACKET.

Reseñas

Reseñas contribuidas por usuarios

Reseñas de usuarios de WorldCat (1)

www.parkanorgebutikk.com Rabatt moncler Dame vests salg nettbutikk

por parkanorgebutikk (Publicadas por usuario de WorldCat 2012-06-24) Excelente Permalink

Moncler jakker, kåper og vester for menn og kvinner med uslåelige priser pluss gratis frakt !

<a href="http://www.parkanorgebutikk.com/moncler-dame-vests-c-167.html">http://www.parkanorgebutikk.com/moncler-dame-vests-c-167.html</a>

  • ¿Le fue útil esta reseña?
  •   
Recuperando reseñas de GoodReads…
Recuperando reseñas de DOGObooks…

Etiquetas

Ser el primero.
Confirmar este pedido

Ya ha pedido este material. Escoja OK si desea procesar el pedido de todos modos.

Datos enlazados


<http://www.worldcat.org/oclc/491221873>
library:oclcnum"491221873"
library:placeOfPublication
library:placeOfPublication
owl:sameAs<info:oclcnum/491221873>
rdf:typeschema:Book
schema:about
schema:about
schema:about
schema:about
schema:about
<http://id.worldcat.org/fast/975545>
rdf:typeschema:Intangible
schema:name"Integrated circuits--Design and construction"@en
schema:about
schema:about
schema:about
<http://id.worldcat.org/fast/1017641>
rdf:typeschema:Intangible
schema:name"Metal oxide semiconductors, Complementary--Design and construction"@en
schema:about
schema:about
<http://id.loc.gov/authorities/subjects/sh2008107701>
rdf:typeschema:Intangible
schema:name"Metal oxide semiconductors, Complementary--Design and construction."@en
schema:bookFormatschema:EBook
schema:contributor
schema:copyrightYear"2009"
schema:datePublished"2009"
schema:description"1. Introduction.1.1 DFM - Value proposition.1.2 Deficiencies in Boolean-based Design Rules in the sub-wavelength regime [6].1.3 Impact of Variability on Yield and Performance.1.4 The industry challenge - disappearing process window.1.5 Mobility enhancement techniques - a new source of variability induced by design process interaction.1.6 Design dependency of chip surface topology.1.7 Newly exacerbated narrow width effect in nano-CMOS nodes.1.8 Well proximity effect.1.9 Scaling beyond 65nm drives the need for model based DFM solutions.1.10 Summary.PART 1: NEWLY EXACERBATED EFFECTS.2. Lithography related Aspects of DFM.2.1 Economic motivations for DFM.2.2 Lithographic tools and techniques for advanced technology nodes.2.3 Lithography limited yield.2.4 Lithography driven DFM Solutions.3. Interaction of layout with transistor performance and stress engineering techniques.3.1 Introduction.3.2 Impact of stress on transistor performance.3.3 Stress propagation.3.4 Stress sources.3.5 Introducing stress into transistors.PART 2: DESIGN SOLUTIONS.4. Signal and Power Integrity.4.1 Introduction.4.2 Interconnect Resistance, Capacitance and Inductance.4.3 Inductance Effects on Interconnect.5. Analog and Mixed Signal Circuit Design for Yield and Manufacturability.5.1 Introduction.5.2 Guidelines.5.3 Device Selection.5.4 Device Size Heart Beat.5.5 Device Matching.5.6 Design Guidelines.5.7 Layout Guidelines.5.8 Test.6. Design for Variability, Performance and Yield.6.1 Introduction.6.2 Impact of variations (introduced by both process and circuit operation) on the design.6.3 Some Parametric Fluctuations with new implications for design .6.4 Process Variations in Interconnects.6.5 Impact of Deep Sub-Micron Integration in SRAMs.6.6 Impact of Layout Styles on Manufacturability, Yield and Scalability.6.7 Design for variations.6.8 Summary.PART 3: THE ROAD TO DFM.7. Nano-CMOS design tools: Beyond model-based analysis and correction.7.1 Introduction.7.2 Electrical Design for Manufacturability (DFM).7.3 Criticality Aware DFM.7.4 On Guardbands, Statistics, and Gaps.7.5 Opportunistic Mindsets.7.6 Futures at o 45nm .7.7 Summary.7.8 References."@en
schema:description""Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also tackle complex issues in the design process to overcome the difficulties, including the use of a functional first silicon to support a predictable product ramp. Moreover, they introduce several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions."--BOOK JACKET."@en
schema:exampleOfWork<http://worldcat.org/entity/work/id/500381407>
schema:genre"Electronic books."@en
schema:inLanguage"en"
schema:name"Nano-CMOS design for manufacturability robust circuit and physical design for sub-65 nm technology nodes"@en
schema:numberOfPages"385"
schema:publisher
schema:url<http://www.myilibrary.com?id=268822>
schema:url<http://app.knovel.com/web/toc.v/cid:kpNCMOSDM2>
schema:url<http://public.eblib.com/EBLPublic/PublicView.do?ptiID=413074_0>
schema:url
schema:url
schema:url<http://public.eblib.com/EBLPublic/PublicView.do?ptiID=413074>
schema:url<http://site.ebrary.com/id/10278707>
schema:url<http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=266156>
schema:workExample
schema:workExample
schema:workExample
schema:workExample

Content-negotiable representations

Cerrar ventana

Inicie una sesión con WorldCat 

¿No tienes una cuenta? Puede fácilmente crear una cuenta gratuita.