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|추가적인 물리적 형식:||Print version:
Nano-CMOS design for manufacturability.
Hoboken, NJ : Wiley, ©2009
|자료 유형:||문서, 인터넷 자료|
|문서 형식:||인터넷 자원, 컴퓨터 파일|
|모든 저자 / 참여자:||
Ban P Wong
|ISBN:||9781615831753 1615831754 9780470382820 0470382821 9780470382813 0470382813|
|설명:||1 online resource (xv, 385 pages) : illustrations|
|내용:||1. Introduction. 1.1 DFM --
Value proposition. 1.2 Deficiencies in Boolean-based Design Rules in the sub-wavelength regime .1.3 Impact of Variability on Yield and Performance. 1.4 The industry challenge --
disappearing process window. 1.5 Mobility enhancement techniques --
a new source of variability induced by design process interaction. 1.6 Design dependency of chip surface topology. 1.7 Newly exacerbated narrow width effect in nano-CMOS nodes. 1.8 Well proximity effect. 1.9 Scaling beyond 65nm drives the need for model based DFM solutions. 1.10 Summary. PART 1: NEWLY EXACERBATED EFFECTS. 2. Lithography related Aspects of DFM. 2.1 Economic motivations for DFM. 2.2 Lithographic tools and techniques for advanced technology nodes. 2.3 Lithography limited yield. 2.4 Lithography driven DFM Solutions. 3. Interaction of layout with transistor performance and stress engineering techniques. 3.1 Introduction. 3.2 Impact of stress on transistor performance. 3.3 Stress propagation. 3.4 Stress sources. 3.5 Introducing stress into transistors. PART 2: DESIGN SOLUTIONS. 4. Signal and Power Integrity. 4.1 Introduction. 4.2 Interconnect Resistance, Capacitance and Inductance. 4.3 Inductance Effects on Interconnect. 5. Analog and Mixed Signal Circuit Design for Yield and Manufacturability. 5.1 Introduction. 5.2 Guidelines. 5.3 Device Selection. 5.4 Device Size Heart Beat. 5.5 Device Matching. 5.6 Design Guidelines. 5.7 Layout Guidelines. 5.8 Test. 6. Design for Variability, Performance and Yield. 6.1 Introduction. 6.2 Impact of variations (introduced by both process and circuit operation) on the design. 6.3 Some Parametric Fluctuations with new implications for design .6.4 Process Variations in Interconnects. 6.5 Impact of Deep Sub-Micron Integration in SRAMs. 6.6 Impact of Layout Styles on Manufacturability, Yield and Scalability. 6.7 Design for variations. 6.8 Summary. PART 3: THE ROAD TO DFM. 7. Nano-CMOS design tools: Beyond model-based analysis and correction. 7.1 Introduction. 7.2 Electrical Design for Manufacturability (DFM).7.3 Criticality Aware DFM. 7.4 On Guardbands, Statistics, and Gaps. 7.5 Opportunistic Mindsets. 7.6 Futures at o 45nm .7.7 Summary. 7.8 References.
|책임:||Ban Wong [and others].|
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