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A primer on hardware prefetching

Author: Babak Falsafi; Thomas F Wenisch
Publisher: [San Rafael, California] : Morgan & Claypool Publishers, [2014] ©2014
Series: Synthesis lectures in computer architecture, #28.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Database:WorldCat
Summary:
Since the 1970's, microprocessor-based digital platforms have been riding Moore's law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Falsafi, Babak.
Primer on hardware prefetching.
[S.l.] : Morgan & Claypool, 2014
(OCoLC)881314050
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Babak Falsafi; Thomas F Wenisch
ISBN: 9781608459537 1608459535
OCLC Number: 881524638
Description: 1 online resource (xiv, 53 pages) : illustrations.
Contents: 1. Introduction --
1.1 The memory wall --
1.2 Prefetching --
1.2.1 Predicting addresses --
1.2.2 Prefetch lookahead --
1.2.3 Placing prefetched values. 2. Instruction prefetching --
2.1 Next-line prefetching --
2.2 Fetch-directed prefetching --
2.3 Discontinuity prefetching --
2.4 Prescient fetch --
2.5 Temporal instruction fetch streaming --
2.6 Return-address stack-directed instruction prefetching --
2.7 Proactive instruction fetch. 3. Data prefetching --
3.1 Stride and stream prefetchers for data --
3.2 Address-correlating prefetchers --
3.2.1 Jump pointers --
3.2.2 Pair-wise correlation --
3.2.3 Markov prefetcher --
3.2.4 Improving lookahead via prefetch depth --
3.2.5 Improving lookahead via dead block prediction --
3.2.6 Addressing on-chip storage limitations --
3.2.7 Global history buffer --
3.2.8 Stream chaining --
3.2.9 Temporal memory streaming --
3.2.10 Irregular stream buffer --
3.3 Spatially correlated prefetching --
3.3.1 Delta-correlated lookup --
3.3.2 Global history buffer PC-localized/delta-correlating (GHB PC/DC) --
3.3.3 Code-correlated lookup --
3.3.4 Spatial footprint prediction --
3.3.5 Spatial pattern prediction --
3.3.6 Stealth prefetching --
3.3.7 Spatial memory streaming --
3.3.8 Spatio-temporal memory streaming --
3.4 Execution-based prefetching --
3.4.1 Algorithm summarization --
3.4.2 Helper-thread and helper-core approaches --
3.4.3 Run-ahead execution --
3.4.4 Context restoration --
3.4.5 Computation spreading --
3.5 Prefetch modulation and control --
3.6 Software approaches. 4. Concluding remarks --
Bibliography --
Author biographies.
Series Title: Synthesis lectures in computer architecture, #28.
Responsibility: Babak Falsafi, EPFL, Thomas F. Wenisch, University of Michigan.

Abstract:

Since the 1970's, microprocessor-based digital platforms have been riding Moore's law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance between the processors and memory has led to a phenomenon referred to as the "Memory Wall." To overcome the memory wall, designers have resorted to a hierarchy of cache memory levels, which rely on the principal of memory access locality to reduce the observed memory access time and the performance gap between processors and memory. Unfortunately, important workload classes exhibit adverse memory access patterns that baffle the simple policies built into modern cache hierarchies to move instructions and data across cache levels. As such, processors often spend much time idling upon a demand fetch of memory blocks that miss in higher cache levels. Prefetching--predicting future memory accesses and issuing requests for the corresponding memory blocks in advance of explicit accesses--is an effective approach to hide memory access latency. There have been a myriad of proposed prefetching techniques, and nearly every modern processor includes some hardware prefetching mechanisms targeting simple and regular memory access patterns. This primer offers an overview of the various classes of hardware prefetchers for instructions and data proposed in the research literature, and presents examples of techniques incorporated into modern microprocessors.

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