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Resource efficient LDPC decoders : from algorithms to hardware architectures

Author: Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz
Publisher: London : Academic Press, an imprint of Elsevier, [2018] ©2018
Edition/Format:   eBook : Document : English
Summary:
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: Modern techniques  Read more...
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Genre/Form: Electronic books
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz
ISBN: 9780128112564 0128112565
OCLC Number: 1014019259
Description: 1 online resource : color illustrations
Contents: Machine generated contents note: ch. 1 Introduction --
1.1. Error Correction in Digital Communication System --
1.2. Forward Error Correction Codes --
References --
ch. 2 Overview of LDPC codes --
2.1. Origin of LDPC Codes --
2.2. Types of LDPC Codes --
2.2.1. Regular and irregular codes --
2.2.2. Random and pseudo-random codes --
2.2.3. Structured and unstructured codes --
2.3. Terminologies in LDPC Codes --
2.3.1. LDPC code parameters --
2.3.2. Simulation parameters --
2.3.3. Performance metrics --
2.4. Summary --
References --
ch. 3 Structure and flexibility of LDPC codes --
3.1. LDPC Code Construction --
3.1.1. Progressive edge growth codes --
3.1.2. Quasi-cyclic codes --
3.1.3. Spatially-coupled codes --
3.1.4. Repeat-accumulate codes --
3.2. Flexible Codes --
3.2.1. Structure of the matrix --
3.2.2. Construction technique --
3.2.3. Standard matrix configurations --
3.2.4. Visual analysis --
3.2.5. Performance analysis --
3.3. Summary --
References --
ch. 4 LDPC decoding algorithms --
4.1. Standard Decoding Algorithms --
4.1.1. Bit-Flip algorithm --
4.1.2. Sum-Product algorithm --
4.1.3. Min-Sum algorithm --
4.1.4. Stochastic algorithm --
4.2. Reduced Complexity Algorithms --
4.2.1. Simplified message passing --
4.2.2. Modified Min-Sum --
4.3. Performance Analysis of Simplified Algorithms --
4.3.1. Extraction of optimized parameters --
4.3.2. Performance comparison --
4.4. Summary --
References --
ch. 5 LDPC decoder architectures --
5.1. Common Hardware Architectures --
5.1.1. Fully-parallel --
5.1.2. Fully-serial --
5.1.3. Partially-parallel --
5.2. Review of Practical LDPC Decoders --
5.3. Summary --
References --
ch. 6 Hardware implementation of LDPC decoders --
6.1. Decoder Design Methodology --
6.1.1. Design and implementation --
6.1.2. Performance measurement --
6.2. Prototyping LDPC Codes in Hardware --
6.3. Implementation of Hardware Efficient Decoder --
6.3.1. Fully-parallel architecture --
6.3.2. Partially-parallel architecture --
6.3.3. Performance analysis --
6.4. Design Space Exploration --
6.4.1. Decoding performance --
6.4.2. Hardware performance --
6.5. Summary --
References --
ch. 7 LDPC decoders in multimedia communication --
7.1. Image Communication Using LDPC Codes --
7.2. Performance Analysis --
7.2.1. Quality of the reconstructed BMP images --
7.2.2. Quality of the reconstructed JPEG images --
7.2.3. Reconstructed JPEG images for various decoders --
7.3. Summary --
References --
ch. 8 Prospective LDPC applications --
8.1. Wireless Communication --
8.2. Optical Communication --
8.3. Flash Memory Devices --
References.
Responsibility: Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz.

Abstract:

This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementationHow to reduce computational complexity and power consumption using computer aided design techniquesAll aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs.

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