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Resource efficient LDPC decoders : from algorithms to hardware architectures

Author: Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz
Publisher: London : Academic Press, an imprint of Elsevier, [2018] ©2018
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: Modern techniques  Read more...
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Genre/Form: Electronic books
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz
ISBN: 9780128112564 0128112565
OCLC Number: 1014019259
Description: 1 online resource : color illustrations
Contents: Introduction --
Overview of LDPC codes --
Structure and flexibility of LDPC codes --
LDPC decoding algorithms --
LDPC decoder architectures --
Hardware implementation of LDPC decoders --
LDPC decoders in multimedia communication --
Prospective LDPC applications.
Responsibility: Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz.

Abstract:

This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementationHow to reduce computational complexity and power consumption using computer aided design techniquesAll aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs.

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