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Robustness and usability in modern design flows

Author: Görschwin Fey; Rolf Drechsler
Publisher: Dordrecht : Springer, 2008.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

The size of technically producible integrated circuits increases continuously, but the ability to design and verify these circuits does not keep up. Using a visionary approach, this book analyzes the  Read more...

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Document Type: Book
All Authors / Contributors: Görschwin Fey; Rolf Drechsler
ISBN: 9781402065354 1402065353
OCLC Number: 166372353
Description: xiii, 166 pages : illustrations ; 25 cm
Contents: Dedication. List of Figures. List of Tables. Preface.1. Introduction.2. Preliminaries. 2.1 Boolean Reasoning. 2.2 Circuits. 2.3 Formal Verification. 2.4 Automatic Test Pattern Generation.3. Algorithms and Data Structures. 3.1 Combining SAT and BDD Provers. 3.2 Summary and Future Work.4. Synthesis. 4.1 Synthesis of SystemC. 4.2 Synthesis for Testability. 4.3 Summary and Future Work.5. Property Generation. 5.1 Detecting Gaps in Testbenches. 5.2 Design Understanding. 5.3 Summary and Future Work.6. Diagnosis. 6.1 Comparing SAT-based and Simulation-based Approaches. 6.2 Generating Counterexamples for Diagnosis. 6.3 Debugging Properties. 6.4 Summary and Future Work.7. Summary and Conclusions.References. Index of Symbols. Index.
Responsibility: by Görschwin Fey and Rolf Drechsler.

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From the reviews:"The authors, Gorschwin Fey and Rolf Drechsler, have identified several deficiencies in the design steps and manual fault diagnosis and have proposed a number of methods to alleviate Read more...

 
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