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Second International Symposium on High-Performance Computer Architecture : proceedings, February 3-7, 1996, San Jose, California

Author: IEEE Computer Society. Technical Committee on Computer Architecture.
Publisher: Los Alamitos, CA : IEEE Computer Society Press, ©1996.
Edition/Format:   Print book : Conference publication : EnglishView all editions and formats
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Genre/Form: Conference papers and proceedings
Congresses
Material Type: Conference publication, Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: IEEE Computer Society. Technical Committee on Computer Architecture.
ISBN: 0818672374 9780818672378 0818672390 9780818672392
OCLC Number: 35035578
Description: xii, 335 pages : illustrations ; 28 cm
Contents: Keynote Speech: Mysteries of the Intel Pentium Pro / Bob Colwell --
Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers / M. Karlsson and P. Stenstrom --
Improving Release-Consistent Shared Virtual Memory Using Automatic Update / L. Iftode, C. Dubnicki, E. W. Felten and K. Li --
A Comparison of Entry Consistency and Lazy Release Consistency Implementations / S. V. Adve, A. L. Cox, S. Dwarkadas, R. Rajamony and W. Zwaenepoel --
Register File Design Considerations in Dynamically Scheduled Processors / K. I. Farkas, N. P. Jouppi and P. Chow --
Co-Scheduling Hardware and Software Pipelines / R. Govindarajan, E. R. Altman and G. R. Gao --
Representative Traces for Processor Models with Infinite Cache / V. S. Iyengar, L. H. Trevillyan and P. Bose The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors / B. A. Nayfeh, K. Olukotun and J. P. Singh --
Improving the Data Cache Performance of Multiprocessor Operating Systems / C. Xia and J. Torrellas --
Bus-Based COMA --
Reducing Traffic in Shared-Bus Multiprocessors / A. Landin and F. Dahlgren --
RMB --
A Reconfigurable Multiple Bus Network / H. ElGindy, A. K. Somani, H. Schroder, H. Schmeck and A. Spray --
On the Multiplexing Degree Required to Embed Permutations in a Class of Networks with Direct Interconnects / C. Qiao and Y. Mei --
Shuffle-Ring: Overcoming the Increasing Degree of Hypercube / G. Chen and F. C. M. Lau --
Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters / E. P. Markatos and M. G. H. Katevenis --
Protected, User-level DMA for the SHRIMP Network Interface / M. A. Blumrich, C. Dubnicki, E. W. Felten and K. Li --
Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory / L. I. Kontothanassis and M. L. Scott --
Fault-Tolerant Multicast Routing in the Mesh with No Virtual Channels / R. Libeskind-Hadas, K. Watkins and T. Hehre --
A Topology-Independent Generic Methodology for Deadlock-Free Wormhole Routing / H. Park and D. P. Agrawal --
Fault-Tolerance with Multimodule Routers / S. Chalasani and R. V. Boppana --
Multitasking and Multithreading on a Multiprocessor with Virtual Shared Memory / H. L. Muller, P. W. A. Stallard and D. H. D. Warren --
A Cache Coherency Protocol for Optically Connected Parallel Computer Systems / J. A. Reisner and T. S. Wailes --
Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses / W.-J. Yang, R. Sridhar and V. Demjanenko Predictive Sequential Associative Cache / B. Calder, D. Grunwald and J. Emer --
Distributed Prefetch-buffer/Cache Design for High-Performance Memory Systems / T. Alexander and G. Kedem --
Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads / Z. Cuetanovic and D. Bhandarkar --
Decoupled Vector Architectures / R. Espasa and M. Valero --
Performance Study of a Multithreaded Superscalar Microprocessor / M. Gulati and N. Bagherzadeh --
Two Adaptive Hybrid Cache Coherency Protocols / C. Anderson and A. R. Karlin --
A Shared-bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-chip Multiprocessor / M. Takahashi, H. Takano, E. Kaneko and S. Suzuki --
Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors / A. Raynaud, Z. Zhang and J. Torrellas.
Other Titles: High-Performance Computer Architecture, 1996, proceedings, Second International Symposium on.
High-performance Computer architecture
Responsibility: sponsored by the IEEE Computer Society Technical Committee on Computer Architecture.

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