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Strain-engineered MOSFETs

Author: C K Maiti; T K Maiti
Publisher: Boca Raton : Taylor & Francis, ©2013.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:
"This book brings together new developments in the area of spin-engineered MOSFETs using high-mobility substrates such as SIGe, strained-Si, germanium-on-insulator, and III-V semiconductors. The authors cover the materials aspects, principles, design, fabrication, and applications of advanced devices. They present a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process  Read more...
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Document Type: Book
All Authors / Contributors: C K Maiti; T K Maiti
ISBN: 9781466500556 1466500557
OCLC Number: 809563361
Description: xix, 300 pages : illustrations ; 24 cm
Contents: 1. Introduction --
1.1. Technology Scaling --
1.2. Substrate-Induced Strain Engineering --
1.3. Process-Induced Stress Engineering --
1.4. Electronic Properties of Strained Semiconductors --
1.5. Strain-Engineered MOSFETs --
1.6. Noise in Strain-Engineered Devices --
1.7. Technology CAD of Strain-Engineered MOSFETs --
1.8. Reliability of Strain-Engineered MOSFETs --
1.9. Process Compact Modelling --
1.10. Process-Aware Design --
1.11. Summary --
Additional Reading --
2. Substrate-Induced Strain Engineering in CMOS Technology --
2.1. Substrate Engineering --
2.2. Strained SiGe Film Growth --
2.3. Strained SiGe:C Film Growth --
2.4. Strained Si Films on Relaxed Si1-xGex --
2.5. Strained Si on SOI --
2.6. Strained Ge Film Growth --
2.7. Strained Ge MOSFETs --
2.8. Heterostructure SiGe/SiGe:C Channel MOSFETs --
2.8.1. Band Alignment --
2.8.2. Mobility Enhancement --
2.8.3. Double Quantum Well p-MOSFETs --
2.9. Strained Si MOSFETs --
2.10. Hybrid Orientation Technology --
2.10.1. Device Simulation --
2.11. Summary --
Review Questions --
References --
3. Process-Induced Stress Engineering in CMOS Technology --
3.1. Stress Engineering --
3.2. Si1-xGex in Source/Drain --
3.3. Si1-yCy in Source/Drain --
3.4. Shallow Trench Isolation (STI) --
3.5. Contact Etch Stop Layer (CESL) --
3.6. Silicidation --
3.7. Stress Memorisation Technique (SMT) --
3.8. Global vs. Local Strain --
3.9. BEOL Stress: Through-Silicon Via --
3.10. TSV Modelling --
3.11. Summary --
Review Questions --
References --
4. Electronic Properties of Strain-Engineered Semiconductors --
4.1. Basics of Stress Engineering --
4.1.1. Stress --
4.2. Stress-Strain Relationships --
4.2.1. Modelling of Stress Generation --
4.3. Strain-Engineered MOSFETs: Current --
4.4. Energy Gap and Band Structure --
4.4.1. Bulk Si Band Structure --
4.5. Silicon Conduction Band --
4.6. Silicon Valence Band --
4.7. Band Structure under Stress --
4.8. Piezoresistive Mobility Model --
4.9. Strain-Induced Mobility Model --
4.9.1. Strain-Induced Mobility Model under Electron-Phonon Interaction --
4.9.2. Strain-Induced Interaction Potential Scattering by Acoustic Phonon --
4.9.3. Transition Probability for Acoustic Phonon Scattering --
4.9.4. Strain-Induced Scattering Matrix --
4.9.5. Relaxation Time for Acoustic Phonon Scattering --
4.10. Implementation of Mobility Model --
4.11. Summary --
Review Questions --
References --
5. Strain-Engineered MOSFETs --
5.1. Process Integration --
5.1.1. Power Consumption --
5.1.2. Leakage Current --
5.1.3. Metal Gate Electrodes --
5.1.4. High-k Gate Dielectrics --
5.2. Multigate Transistors --
5.3. Double-Gate MOSFET --
5.4. ?-FinFET --
5.5. Tri-Gate FinFET --
5.6. FinFETs Using Gate-Induced Stress --
5.7. Stress-Engineered FinFETs --
5.8. Layout Dependence --
5.9. Summary --
Review Questions --
References --
6. Noise in Strain-Engineered Devices / C. Mukherjee --
6.1. Noise Mechanisms --
6.2. Fundamental Noise Sources --
6.2.1. Thermal Noise --
6.2.2. Shot Noise --
6.2.3. Generation-Recombination Noise --
6.2.4. Random Telegraph Signal (RTS) Noise --
6.2.5. 1/f Noise --
6.3. 1/f Noise in MOSFETs --
6.3.1. Number Fluctuations --
6.3.2. Mobility Fluctuations --
6.4. Noise Characterisation in MOSFETs --
6.4.1. Noise Measurements as a Diagnostic Tool --
6.5. Strain Effects on Noise in MOSFETs --
6.5.1. n-MOSFET under Tensile Stress --
6.5.2. n-MOSFET under Compressive Stress --
6.5.3. p-MOSFET under Compressive Stress --
6.5.4. Number Fluctuation Model under Strain --
6.5.4.1. Mechanisms for Change in Noise PSD under Strain --
6.6. Noise in Strain-Engineered MOSFETs --
6.6.1. Low-Frequency Noise Measurements --
6.6.2. Strained Si MOSFETs --
6.7. Noise in Multigate FETs --
6.7.1. Noise in Tri-Gate FinFET --
6.8. Noise in Silicon Nanowire Transistors (SNWTs) --
6.9. Noise in Heterojunction Bipolar Transistors --
6.9.1. Low-Frequency Noise Measurement of SiGe:C HBT --
6.10. Summary --
Review Questions --
References --
7. Technology CAD of Strain-Engineered MOSFETs --
7.1. TCAD Calibration --
7.2. Simulation of Strain-Engineered MOSFETs --
7.2.1. Strain-Engineered p-MOSFETs --
7.2.2. Strain-Engineered n-MOSFETs --
7.3. DC Performance --
7.4. AC Performance --
7.5. Hybrid Orientation Technology for Strain-Engineered MOSFETs --
7.6. Simulation of Embedded SiGe MOSFETs --
7.7. Summary --
Review Questions --
References --
8. Reliability and Degradation of Strain-Engineered MOSFETs --
8.1. NBTI in Strain-Engineered p-MOSFETs --
8.1.1. Quasi-2D Coulomb Mobility Model --
8.2. Simulation of NBTI in p-MOSFETs --
8.3. HCI in Strain-Engineered n-MOSFETs --
8.3.1. Degradation Mechanisms --
8.4. Simulation of HCI in n-MOSFETs --
8.5. Reliability Issues in FinFETs --
8.6. Summary --
Review Questions --
References --
9. Process Compact Modelling of Strain-Engineered MOSFETs --
9.1. Process Variation --
9.2. Predictive Technology Modelling --
9.2.1. PTM for FinFET --
9.3. Process-Aware Design for Manufacturing --
9.4. Process Compact Model --
9.4.1. PCM Analysis --
9.5. Process-Aware SPICE Parameter Extraction --
9.5.1. Circuit Modelling --
9.6. Summary --
Review Questions --
References --
10. Process-Aware Design of Strain-Engineered MOSFETs --
10.1. Process Design Co-Optimisation --
10.2. Classifications of Variation --
10.3. Designs for Manufacturing and Yield Optimisation --
10.3.1. Process Optimisation --
10.3.2. Process Parameterisation --
10.3.3. Smoothness and Sensitivity Analysis --
10.3.4. Visual Optimisation --
10.4. Performance Optimisation --
10.5. Manufacturability Optimisation --
10.6. Summary --
Review Questions --
References --
11. Conclusions.
Responsibility: C.K. Maiti, T.K. Maiti.
More information:

Abstract:

"This book brings together new developments in the area of spin-engineered MOSFETs using high-mobility substrates such as SIGe, strained-Si, germanium-on-insulator, and III-V semiconductors. The authors cover the materials aspects, principles, design, fabrication, and applications of advanced devices. They present a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization"--

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"... an immensely useful book for the researcher in this field and even for some like me who do not work exactly in this area. Any scientist interested in strain modulation of device properties will Read more...

 
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