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Superscalar microprocessor design

Author: Mike Johnson
Publisher: Englewood Cliffs, N.J. : Prentice Hall, ©1991.
Series: Prentice Hall series in innovative technology.
Edition/Format:   Print book : EnglishView all editions and formats
Summary:

A comprehensive technical tutorial on the design of general-purpose superscalar microprocessors.

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Genre/Form: Superskalarer Mikroprozessor
Additional Physical Format: Online version:
Johnson, Mike, 1953-
Superscalar microprocessor design.
Englewood Cliffs, N.J. : Prentice Hall, ©1991
(OCoLC)645796272
Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Mike Johnson
ISBN: 0138756341 9780138756345
OCLC Number: 22451341
Description: xxiv, 288 pages : illustrations ; 25 cm.
Contents: Beyond Pipelining, CISC, and RISC --
An Introduction to Superscalar Concepts --
Fundamental Limitations --
True Data Dependencies --
Procedural Dependencies --
Resource Conflicts --
Instruction Parallelism and Machine Parallelism --
Instruction Issue and Machine Parallelism --
In-Order Issue with In-Order Completion --
In-Order Issue with Out-of-Order Completion --
Out-of-Order Issue with Out-of-Order Completion --
Storage Conflicts and Register Renaming --
Related Concepts: Vliw and Superpipelined Processors --
Very-Long-Instruction-Word Processors --
Superpipelined Processors --
Hybrid Techniques --
Unrelated Parallel Schemes --
Developing an Execution Model --
Simulation Technique --
Benchmarking Performance --
Basic Observations on Hardware Design --
The Philosophy of the Standard Processor --
Instruction Parallelism of the Benchmarks --
Machine Parallelism --
The Design of the Standard Processor --
Basic Organization --
Out-of-Order Issue --
Register Renaming --
Loads and Stores --
The Performance of the Model --
The Real Performance Limit: Procedural Dependencies --
Instruction Fetching and Decoding --
Branches and Instruction-Fetch Inefficiencies --
Improving Fetch Efficiency --
Scheduling Delayed Branches --
Branch Prediction --
Aligning and Merging --
Simulation Results and Observations --
Multiple-Path Execution --
Implementing Hardware Branch-Prediction --
Basic Organization --
Setting and Interpreting Cache Entries --
Predicting Branches --
Hardware and Performance Costs --
Implementing A Four-Instruction Decoder --
Implementing Branches --
Number of Pending Branches --
Order of Branch Execution --
Simplifying Branch Decoding --
Reducing the Penalty of Procedural Dependencies: Observations --
The Role of Exception Recovery --
Buffering State Information for Restart --
In-Order, Lookahead, and Architectural State --
Checkpoint Repair --
History Buffer --
Reorder Buffer --
Future File --
Restart Implementation and Effect on Performance --
Mispredicted Branches --
Exceptions --
The Effect of Recovery Hardware on Performance --
Processor Restart: Observations --
Register Dataflow --
Dependency Mechanisms --
The Value of Register Renaming --
Register Renaming with a Reorder Buffer --
Renaming with a Future File: Tomasulo's Algorithm --
Enforcing Dependencies with Interlocks --
Copying Operands to Avoid Antidependencies --
Partial Renaming --
Special Registers and Instruction Side Effects --
Result Buses and Arbitration --
Result Forwarding --
Supplying Instruction Operands: Observations --
Out-of-Order Issue --
Reservation Stations --
Reservation Station Operation --
Performance Effect of Reservation-Station Size --
A Simpler Implementation of Reservation Stations --
Implementing a Central Instruction Window --
The Dispatch Stack --
The Register Update Unit --
Using a Reorder Buffer to Simplify the Central Window --
Operand Buses from a Central Window --
The Complexity of a Central Window --
Out-of-Order Issue: Observations --
Memory Dataflow --
Ordering of Loads and Stores --
Total Ordering of Loads and Stores --
Load Bypassing of Stores --
Load Bypassing with Forwarding --
Performance of the Load/Store Policy --
Load Side Effects --
Addressing and Dependencies --
Limiting Address Logic with a Preaddress Buffer or Central Instruction Window --
Effect of Store-Buffer Size --
Memory Dependency Checking --
What is More Load/Store Parallelism Worth? --
Esoterica: Multiprocessing Considerations --
Accessing External Data: Observations --
Complexity and Controversy --
A Brief Glimpse at Design Complexity --
Allocating Processor Resources --
Instruction Decode --
Instruction Completion --
The Painful Truth --
Major Hardware Features --
Hardware Simplifications --
Is the Complexity Worth it? --
Basic Software Scheduling --
The Benefit of Scheduling --
Impediments to Efficient Execution --
How Scheduling Can Help --
Is the Benefit Significant? --
Program Information Needed for Scheduling --
Dividing Code into Basic Blocks --
The Dataflow Graph of a Basic Block --
The Precedence Graph --
The Concept of the Critical Path --
The Resource Reservation Table --
Relationship of the Scheduler and the Compiler --
Interaction of Register Allocation and Scheduling --
Scheduling During Compilation Versus After Compilation --
Algorithms for Scheduling Basic Blocks --
The Expense of an Optimum Schedule --
List Scheduling --
The Effect of Scheduling Order --
Other Scheduling Alternatives --
Revisiting the Hardware --
Software Scheduling Across Branches --
Trace Scheduling --
A Simple Example of Trace Scheduling --
Using Compensation Code to Recover from Incorrect Predictions --
Trace Scheduling an Entire Program --
Correctness of Trace Scheduling --
Loop Unrolling --
Unrolling to Improve the Loop Schedule --
Unrolling with Data-Dependent Branches --
Software Pipelining --
Pipelining Operations from Different Loop Iterations --
Software-Pipelining Techniques --
Filling and Flushing the Pipeline: The Prologue and Epilogue --
Register Renaming in the Software-Pipelined Loop --
Global Code Motion --
Out-of-Order Issue and Scheduling Across Branches --
Evaluating Alternatives: A Perspective on Superscalar Microprocessors --
The Case for Software Solutions --
Instruction Formats to Simplify Hardware --
Instruction Formats for Scheduling Across Branches --
The Costs and Risks of Software Solutions --
The Case for Hardware Solutions --
Two Models of Performance Growth --
Estimating Risks in a Performance-Oriented Design --
Estimating Risks in a Cost-Sensitive Design --
Putting Risks in Perspective --
A Superscalar 386 --
The Architecture --
Instruction Format --
Register Dependencies --
Memory Accesses --
Complex Instructions --
The Implementation --
Out-of-Order Microinstruction Issue --
Overlapping Microinstruction Sequences --
Superscalar Execution of a "RISC Core" Instruction Set.
Series Title: Prentice Hall series in innovative technology.
Responsibility: Mike Johnson.

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