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Switch-level timing simulation of MOS VLSI circuits

Author: Vasant B Rao
Publisher: Boston : Kluwer Academic Publishers, ©1989.
Series: Kluwer international series in engineering and computer science, SECS 66.; Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing.
Edition/Format:   Print book : EnglishView all editions and formats
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Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and  Read more...

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Genre/Form: MOS-VLSI-Schaltung
Document Type: Book
All Authors / Contributors: Vasant B Rao
ISBN: 0898383021 9780898383027
OCLC Number: 18557247
Description: x, 209 pages : illustrations ; 25 cm.
Contents: 1. Introduction.- 2. Overview of Simulation Techniques.- 2.1 Analog vs Digital Simulation.- 2.2 Gate-Level Simulation.- 2.3 Switch-Level Logic Simulation.- 2.4 Mixed-Mode or Hybrid Simulation.- 2.5 Switch-Level Timing Simulation.- 3. Mos Network Partitioning and Ordering.- 3.1 MOS Network Components and Models.- 3.2 Partitioning the MOS Network into Blocks.- 3.2.1 Review of Graph Theory.- 3.2.2 Blocks of an MOS Network.- 3.2.3 Partitioning Algorithm and Its Complexity.- 3.2.4 A CMOS Example.- 3.3* Partitioning into Driver and Pass Transistors.- 3.3.1 Motivation.- 3.3.2 Formal Definitions.- 3.3.3 Partitioning Algorithm.- 3.3.4 An NMOS Example.- 3.3.5 Modifications for CMOS Circuits.- 3.4 Ordering of Partitioned Blocks.- 3.4.1 Directed Graphs.- 3.4.2 Presence of Feedback and Its Detection.- 3.4.3 An Example to Illustrate Ordering.- 3.5 Conclusions.- 4. Switch-Level Timing Simulation.- 4.1 Overview.- 4.2 Waveform Representation.- 4.3 Simulation Algorithm.- 4.4 Deriving Inverter Voltage Equations.- 4.4.1 Equations for Switching Inputs.- 4.4.2 Equations for Fixed Inputs.- 4.4.3 Using the Equations.- 4.5 Determining the dc Output Voltage.- 4.6 Mapping Complex Blocks to Primitives.- 4.6.1 Transistor Reduction Basis.- 4.6.2 Subcircuit Reduction Algorithm.- 4.7 Parasitics.- 4.8 Sample Subcircuit Processing.- 4.8.1 Simple CMOS Inverter.- 4.8.2 CMOS NAND Gate.- 4.8.3 NMOS Inverter Driving a Pass Transistor.- 5. Simulating Strongly Connected Components.- 5.1 Waveform Relaxation vs Time-point Relaxation.- 5.2 Dynamic Windowing.- 6. Performance of Idsim2.- References.- About The Authors.
Series Title: Kluwer international series in engineering and computer science, SECS 66.; Kluwer international series in engineering and computer science., VLSI, computer architecture, and digital signal processing.
Responsibility: by Vasant B. Rao [and others].

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