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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs

Author: Balsha R Stanisic; Rob A Rutenbar; L Richard Carley
Publisher: Boston, MA : Springer US, 1996.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
The move to higher levels of integration has increased the fraction of application-specific integrated circuit (ASIC) designs containing both analog and digital circuits. While the die area for the analog portion of these chips is modest, the design time is often significant. This has motivated the development of automated analog physical design tools for cell-level place-and-route and system-level  Read more...
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Genre/Form: Electronic books
Additional Physical Format: Print version:
Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Balsha R Stanisic; Rob A Rutenbar; L Richard Carley
ISBN: 9781461313991 1461313996
OCLC Number: 852790299
Description: 1 online resource (208 pages)
Contents: 1 Introduction --
1.1 Focus --
1.2 Motivation --
1.3 Research Overview --
1.4 Preview of Results --
1.5 Book Organization --
2 Power Distribution Noise and Physical Design Methods --
2.1 Analog Design Problem Characteristics --
2.2 Design Style Concerns --
2.3 Analog Power Distribution Design Concerns --
2.4 Previous Research in Power Distribution Synthesis --
2.5 Critical Analysis --
2.6 Concluding Remarks --
3 Physical Design and Optimization --
3.1 New Optimization-based Strategy --
3.2 Design Style Selection --
3.3 Power Bus Topology Selection and Sizing --
3.4 Power I/O Cell Assignment --
3.5 Simultaneous Power Bus and I/O Cell Optimization --
3.6 Review of Simulated Annealing --
3.7 Simulated Annealing Formulation --
3.8 Concluding Remarks --
4 DC, AC, and Transient Electrical Models and Analysis --
4.1 Electrical Formulation Objectives --
4.2 Mapping Power Bus and I/O Cell Geometry to Electricity --
4.3 Modeling Macrocells --
4.4 Modeling Interconnect --
4.5 Modeling Chip Substrate --
4.6 DC Behavior Evaluation Methods --
4.7 AC and Transient Behavior Evaluation Methods --
4.8 Review of Asymptotic Waveform Evaluation (AWE) --
4.9 AWE-based Single Input Switching Behavior --
4.10 AWE-based Simultaneous Switching Behavior --
4.11 Concluding Remarks --
5 Experimental Results --
5.1 Experimental Plan --
5.2 Example Nonconvex --
5.3 Example Analog 1 --
5.4 Example Mixed-Signal1 --
5.5 Example Mixed-Signal2 --
5.6 Example Mixed-Signal3 --
5.7 Example Config 1 --
5.8 Example Stanford --
5.9 Example Mixed-Signal4 --
5.10 Example CMU --
5.11 SQP and Annealing, Revisited --
5.12 Concluding Remarks --
6 Conclusions --
6.1 Summary --
6.2 Contributions --
6.3 Future Directions --
A Symbolic Convolution of Special Waveforms --
A.1 Specialized Waveforms --
A.1.1 Trap --
A.1.2. Sinsq --
A.2 Fundamental Waveforms --
A.2.1 Step --
A.2.2 Ramp --
A.2.3 Cosine --
B Circuit Element Approximation of Chip Substrate --
B.1 Underlying Treatment --
B.2 General Bulk Field Derivation --
B.3 Box Integration.
Responsibility: by Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley.

Abstract:

Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi- vidual segments for each of these wires, the number  Read more...

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   schema:description "The move to higher levels of integration has increased the fraction of application-specific integrated circuit (ASIC) designs containing both analog and digital circuits. While the die area for the analog portion of these chips is modest, the design time is often significant. This has motivated the development of automated analog physical design tools for cell-level place-and-route and system-level signal-integrity-routing. To date, there is no tool that has specifically addressed the critical design task of synthesizing the power distribution for the analog portion of an analog or mixed-signal ASIC. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs describes algorithms for analog power distribution synthesis and demonstrates their effectiveness. Existing digital power bus synthesis algorithms have failed to address critical concerns for analog circuitry, thus yielding unacceptable results. These tools synthesize only the bus component of power distribution networks and only consider simplified DC aspects of macros and busses. Readers of the companion book in this series, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits (Kluwer Academic Publishers), already recognize the inadequacy of this simplified view of the noise and power distribution problem in mixed-signal integrated circuits. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs addresses power distribution synthesis for mixed-signal integrated circuits. Several key challenges in power distribution design are identified and automated methods to overcome them are described. This book presents a new formulation for the analog power distribution synthesis problem which synthesizes both the power busses power I/O cell assignment by evaluating DC, AC, and transient interaction between the macros, busses, chip substrate, and package. Furthermore, algorithms are introduced which simultaneously optimize power I/O cell assignment, macro cell substrate coupling, power bus topology selection and power bus sizing. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs will be of interest to CAD designers and researchers specializing in physical design, modelling and circuit synthesis."@en ;
   schema:description "1 Introduction -- 1.1 Focus -- 1.2 Motivation -- 1.3 Research Overview -- 1.4 Preview of Results -- 1.5 Book Organization -- 2 Power Distribution Noise and Physical Design Methods -- 2.1 Analog Design Problem Characteristics -- 2.2 Design Style Concerns -- 2.3 Analog Power Distribution Design Concerns -- 2.4 Previous Research in Power Distribution Synthesis -- 2.5 Critical Analysis -- 2.6 Concluding Remarks -- 3 Physical Design and Optimization -- 3.1 New Optimization-based Strategy -- 3.2 Design Style Selection -- 3.3 Power Bus Topology Selection and Sizing -- 3.4 Power I/O Cell Assignment -- 3.5 Simultaneous Power Bus and I/O Cell Optimization -- 3.6 Review of Simulated Annealing -- 3.7 Simulated Annealing Formulation -- 3.8 Concluding Remarks -- 4 DC, AC, and Transient Electrical Models and Analysis -- 4.1 Electrical Formulation Objectives -- 4.2 Mapping Power Bus and I/O Cell Geometry to Electricity -- 4.3 Modeling Macrocells -- 4.4 Modeling Interconnect -- 4.5 Modeling Chip Substrate -- 4.6 DC Behavior Evaluation Methods -- 4.7 AC and Transient Behavior Evaluation Methods -- 4.8 Review of Asymptotic Waveform Evaluation (AWE) -- 4.9 AWE-based Single Input Switching Behavior -- 4.10 AWE-based Simultaneous Switching Behavior -- 4.11 Concluding Remarks -- 5 Experimental Results -- 5.1 Experimental Plan -- 5.2 Example Nonconvex -- 5.3 Example Analog 1 -- 5.4 Example Mixed-Signal1 -- 5.5 Example Mixed-Signal2 -- 5.6 Example Mixed-Signal3 -- 5.7 Example Config 1 -- 5.8 Example Stanford -- 5.9 Example Mixed-Signal4 -- 5.10 Example CMU -- 5.11 SQP and Annealing, Revisited -- 5.12 Concluding Remarks -- 6 Conclusions -- 6.1 Summary -- 6.2 Contributions -- 6.3 Future Directions -- A Symbolic Convolution of Special Waveforms -- A.1 Specialized Waveforms -- A.1.1 Trap -- A.1.2. Sinsq -- A.2 Fundamental Waveforms -- A.2.1 Step -- A.2.2 Ramp -- A.2.3 Cosine -- B Circuit Element Approximation of Chip Substrate -- B.1 Underlying Treatment -- B.2 General Bulk Field Derivation -- B.3 Box Integration."@en ;
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