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|Material Type:||Internet resource|
|Document Type:||Book, Internet Resource|
|All Authors / Contributors:||
H T Kung; Carnegie-Mellon University. Design Research Center.
|Notes:||"A preliminary version of this paper appeared in Proceedings of the 7th International Conference on Pattern Recognition, Montreal, Canada, July 1984, pp. 570-577, as the text of an invited talk"--Added title page.
"January 1984, last revised September 1984"--Added title page.
|Description:||20 pages : illustrations ; 28 cm|
|Responsibility:||by H.T. Kung.|
The prototype has 10 cells, each of which is capable of performing 10 million floating-point operations per second (10 MFLOPS) and is build on a single board using only off-the-shelf components. This 10-cell processor for example can process 1024-point complex FFTs at a rate of one FFT every 600 [mu]s. Under program control, the same processor can perform many other primitive computations in signal, image and vision processing, including two-dimensional convolution and complex matrix multiplication, at a rate of 100 MFLOPS. Together with another processor capable of performing divisions and square roots, the processor can also efficiently carry out a number of difficult matrix operations such as solving covariant linear systems, a crucial computation in real-time adaptive signal processing. This paper outlines the architecture of the Warp processor and describes how the signal processing tasks are implemented on the processor."